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參數(shù)資料
| 型號： | UPD6460GT-101 |
| 英文描述： | On-Screen Display Circuit |
| 中文描述： | 屏幕顯示電路 |
| 文件頁數(shù)： | 20/68頁 |
| 文件大?。?/td> | 301K |
| 代理商： | UPD6460GT-101 |
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20
μ
PD63, 63A, 64
4.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation
instruction. The timer operation instructions for making the timer start operation are shown below:
MOV T0, A
MOV T1, A
MOV T, #data10
MOV T, @R0
The down counter is decremented (–1) in the cycle of 64/f
X
or 128/f
X
Note
. If the value of the down counter becomes
0, the zero detecting circuit generates the timer operation end signal to stop the timer operation. At this time, if
the timer is in HALT mode (HALT #
×
101B) waiting for the timer to stop its operation, the HALT mode is canceled
and the instruction following the HALT instruction is executed. The output of the timer operation end signal is
continued while the down counter is 0 and the timer is stopped. There is the following relational expression between
the timer’s time and the down counter’s set value.
Timer time = (Set value + 1)
×
64/f
X
(or 128/f
X
Note
)
Note
This becomes 128/f
X
if bit 3 of the control register is set (to 1).
By setting 1 for the flag (t
9
) which enables the timer output, the timer can output its operation status from the
S
1
/LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation.
Table 4-1. Timer Output (at t
9
= 1)
S
1
/LED Pin
REM Pin
Timer operating
Timer halting
L
H
H (or carrier output
Note
)
L
Note
The carrier output results if bit 2 of the control register 0 is cleared (to 0).
Figure 4-2. Timer Output (when carrier is not output)
Timer value: (set value + 1)
×
64/f
X
(or 128/f
X
)
LED
REM
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