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參數(shù)資料
| 型號： | UPD6102G |
| 英文描述： | Consumer IC |
| 中文描述： | 消費性IC |
| 文件頁數(shù)： | 26/36頁 |
| 文件大小： | 252K |
| 代理商： | UPD6102G |
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μ
PD61P24
26
DC Programming Characteristics (T
A
= 25
±
5
°
C, V
DD
= 6.0
±
0.25 V, V
PP
= 12.5
±
0.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High-level input voltage
V
IH1
Other than CLK
0.7 V
DD
V
DD
V
V
IH2
CLK
V
DD
–0.5
V
DD
V
Low-level input voltage
V
IL1
Other than CLK
0
0.3 V
DD
V
V
IL2
CLK
0
0.4
V
Input leakage current
I
LI
V
IN
= V
IL
or V
IH
10
μ
A
High-level output voltage
V
OH
I
OH
= –1 mA
V
DD
–1.0
V
Low-level output voltage
V
OL
I
OL
= 1.6 mA
0.4
V
V
DD
supply current
I
DD
30
mA
V
PP
supply current
I
PP
MD0 = V
IL
, MD1 = V
IH
30
mA
Cautions 1. Keep V
PP
to within +13.5 V including the overshoot.
2. Apply V
DD
before V
PP
, and turn it off after V
PP
.
AC Programming Characteristics (T
A
= 25
±
5
°
C, V
DD
= 6.0
±
0.25 V, V
PP
= 12.5
±
0.5 V)
Parameter
Symbol
Note 1
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
Note 2
(vs. MD0
↓
)
t
AS
t
AS
2
μ
s
MD1 setup time (vs. MD0
↓
)
t
M1S
t
OES
2
μ
s
Data setup time (vs. MD0
↓
)
t
DS
t
DS
2
μ
s
Address hold time
Note 2
(vs. MD0
↑
)
t
AH
t
AH
2
μ
s
Data hold time (vs. MD0
↑
)
t
DH
t
DH
2
μ
s
MD0
↑→
data output float delay time
t
DF
t
DF
0
130
ns
V
PP
setup time (vs. MD3
↑
)
t
VPS
t
VPS
2
μ
s
V
DD
setup time (vs. MD3
↑
)
t
VDS
t
VCS
2
μ
s
Initial program pulse width
t
PW
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
OPW
t
OPW
0.95
21.0
ms
MD0 setup time (vs. MD1
↑
)
t
M0S
t
CES
2
μ
s
MD0
↓→
data output delay time
t
DV
t
DV
MD0 = MD1 = V
IL
1
μ
s
MD1 hold time (vs. MD0
↑
)
t
M1H
t
OEH
t
M1H
+ t
M1R
≥
50
μ
s
2
μ
s
MD1 recovery time (vs. MD0
↓
)
t
M1R
t
OR
2
μ
s
Program counter reset time
t
PCR
—
10
μ
s
CLK input high-, low-level widths
t
XH
, t
XL
—
0.125
μ
s
CLK input frequency
f
X
—
4.19
MHz
Initial mode set time
t
I
—
2
μ
s
MD3 setup time (vs. MD1
↑
)
t
M3S
—
2
μ
s
MD3 hold time (vs. MD1
↓
)
t
M3H
—
2
μ
s
MD3 setup time (vs. MD0
↓
)
t
M3SR
—
On reading program memory
2
μ
s
Address
Note 2
→
data output delay time
t
DAD
t
ACC
On reading program memory
2
μ
s
Address
Note 2
→
data output hold time
t
HAD
t
OH
On reading program memory
0
130
ns
MD3 hold time (vs. MD0
↑
)
t
M3HR
—
On reading program memory
2
μ
s
MD3
↓→
data output float delay time
t
DFR
—
On reading program memory
2
μ
s
Reset setup time
t
RES
10
μ
s
Notes 1.
Corresponding symbols of
μ
PD27C256A (the
μ
PD27C256A is a maintenance product).
2.
The internal address signal is incremented by one at the falling edge of CLK input at the third clock.
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