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參數(shù)資料
| 型號： | UPD4992GS-E2 |
| 廠商： | NEC Corp. |
| 英文描述： | 8-Bit Parallel I/O Calendar Clock |
| 中文描述： | 8位并行I / O時(shí)鐘日歷 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 101K |
| 代理商： | UPD4992GS-E2 |
μ
PD4992
8
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
1: CLK adjust
1: Reset
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
1: TP = DISABLE
1: Reset
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
1: TP = L
1: Oscillation
MODE REGISTER (R/W)
HEX
BIN
Mode
0H
0000B
Outputs TP2048 Hz
1H
0001B
Outputs TP1024 Hz
2H
0010B
Outputs TP256 Hz
3H
0011B
Outputs TP64 Hz
4H
0100B
Outputs INT1/2048s
5H
0101B
Outputs INT1/1024s
6H
0110B
Outputs INT1/256s
7H
0111B
Outputs INT1/64s
8H
1000B
Outputs INT1s
9H
1001B
Outputs INT10s
AH
1010B
Outputs INT60s
BH
1011B
Outputs BUSY signal
CH
1100B
Test mode 1
DH
1101B
Test mode 2
EH
1110B
Test mode 3
FH
1111B
Test mode 4
CONTROL REGISTER
Access mode
b3
b2
b1
b0
CLK adjust
Reset
CLK stop
0
0: NOP
0: NOP
0: CLK start
When writing
1: CLK stop
TP enable
*1
INT reset
INT stop
1
0: TP = ENABLE
0: NOP
0: INT start
1: INT stop
*
TP flag
OSC flag
*2
BUSY flag
*3
When reading
(Don’t care)
0: TP = Z
0: No oscillation
0: OFF
1: ON
*1
: When TP enable is 1 (TP = DISABLE), the TP pin becomes high impedance (actually a high level because
a pull up resistor is connected to the TP pin).
But TP flag is not DISABLE in this case.
*2
: If the OSC flag becomes 0 by oscillation stop, the OSC flag remains to be 0 when oscillation is resumed.
To set OSC flag to 1 again, execute CLK reset (if the OSC flag still remains to be 0, oscillation has not been
started again).
Upon initial power application of the
μ
PD4992, 0 is set to the OSC flag.
*3
: The BUSY flag is “1” when the time counter of the
μ
PD4992 is operating (when read is disabled).
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