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參數(shù)資料
| 型號： | UPD488448FB-C80-45-DQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 42/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C80-45-DQ2 |
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Data Sheet M14837EJ3V0DS00
42
μ
PD488448 for Rev. P
Figure 22-1 Control Registers (2/7)
Control Register : CNFGB
Address : 024
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SVER5..0=ssssss
CORG4..0=xxxxx
SPT0
DEVTYP2..0=000
BYTB
Read only register.
Field
Description
SVER5..0
Stepping version. Specifies the mask version number of this device.
Core organization. This field specifies the number of bank (3, 4, 5, or 6 bits), row (9, 10, 11, or 12 bits), and column (5,
6, or 7 bits) address bits. The encoding of this field will be specified in a later version of this document.
CORG4..0
SPT
Split-core. SPT=1 means the core is split, SPT=0 means it is not.
DEVTYP2..0
Device type. DEVTYP=000 means that this device is an RDRAM.
BYT
Byte width. B=1 means the device reads and writes 9-bit memory bytes.B=0 means 8 bits.
Control Register : TEST34
Address : 022
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/write register.
Reset values of TEST34 is zero (from SIO Reset).
This register are used for testing purposes. It must not be read or written after SIO Reset except prior to the SETR/CLRR sequence
when it is written with the value 0040
16
.
After SETR/CLRR it is rewritten to 0000
16
.
Control Register : DEVID
Address : 040
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
DEVID4..0
Read/write register.
Reset value is undefined.
Field
Description
Device Identification register. DEVID4..DEVID0 is compared to DR4..DR0, DC4..DC0, and DX4..DX0 fields for all
memory read or write transactions. This determines which RDRAM is selected for the memory read or write
transaction.
DEVID4..0
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