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參數(shù)資料
| 型號： | UPD4482183GF-A60 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
| 中文描述： | 800萬位CMOS同步快速靜態(tài)存儲器流水線操作雙循環(huán)取消選擇 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 300K |
| 代理商： | UPD4482183GF-A60 |
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1
D
μ
P
TKHKH
TKLKH
TKHAX
TWVKH
TKHWX
TKHEX
TGLQV
TGLQX
TKHQX2
TKHQZ
Q1(A1)
Q1(A2)
Q2(A2)
Q3(A2)
Q4(A2)
Q1(A2)
A1
A2
A3
CLK
/AP
/AC
Address
/ADV
/CEs
Note1
/G
Data In
/BWE
/BWs
TGHQZ
TKHQV
TKHKL
TKHADSX
TADSVKH
TAVKH
TEVKH
TADSVKH
TKHADSX
TADVVKH
TKHADVX
TWVKH
TKHWX
/GW
Data Out
READ CYCLE
Remark
Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
Notes 1.
Note2
Outputs are disabled within two clock cycles after deselect.
3.
If
/GW is set to low level or /BWE is set to low level and one of /BW1 to /BW4 is set to low level,
Q1(A3) is not output.
2.
Q1(A3)
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
High-Z
High-Z
High-Z
Note3
Note3
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