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參數(shù)資料
| 型號： | UPD4481322GF-A75 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT ZEROSB SRAM PIPELINED OPERATION |
| 中文描述： | 800萬位ZEROSB SRAM的流水線操作 |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 404K |
| 代理商： | UPD4481322GF-A75 |
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8
Data Sheet M15562EJ3V0DS
μ
PD4481162, 4481182, 4481322, 4481362
Block Diagrams
[
μ
PD4481162,
μ
PD4481182]
A0 to A18
MODE
CLK
/CKE
ADV
/BW1
/BW2
/WE
/G
/CE
CE2
/CE2
ZZ
Address
register 0
Burst
logic
Write address
register 0
Write registry and
data coherency
control logic
Write
drivers
D
ADV
K
A1
A1’
S
Read
logic
Input
register 0
E
O
E
I/O1 to I/O16
I/OP1, I/OP2
19
17
19
19
19
16/18
16/18
16/18
16/18
Write address
register 1
O
E
Input
register 1
E
16/18
Power down control
K
Memory Cell Array
512 x 16 columns
(8,388,608 bits)
512 x 18 columns
(9,437,184 bits)
1,024 rows
Burst Sequence
[
μ
PD4481162,
μ
PD4481182]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
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