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參數(shù)資料
| 型號(hào)： | UPD444016G5-8Y-7JF |
| 廠商： | NEC Corp. |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 86K |
| 代理商： | UPD444016G5-8Y-7JF |
11
μ
PD444016-Y
Preliminary Data Sheet M15391EJ1V0DS
Write Cycle Timing Chart 3 (/LB, /UB Controlled)
t
WC
t
AS
t
BW
t
WR
t
DW
t
DH
Address (Input)
/LB, /UB (Input)
/WE (Input)
/CS (Input)
High impedance
Data in
High impedance
t
CW
I/O (Input)
t
AW
t
WP
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark
Write operation is done during the overlap time of a low level /CS, /LB and/or /UB, and a low level /WE.
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