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參數(shù)資料
| 型號： | UPD44325182F5-E50-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的2字爆發(fā)運作 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 357K |
| 代理商： | UPD44325182F5-E50-EQ2 |
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18
Preliminary Data Sheet
M16783EJ1V0DS
μ
PD44325082, 44325092, 44325182, 44325362
Read and Write Timing
K
Address
Data in
/K
2
4
6
8
10
1
3
5
7
9
TKH/KH
T/KHKH
C
/C
TKHCH
NOP
READ
READ
READ
WRITE
WRITE
WRITE
TKHKL
TKLKH
Q00
Q20
Data out
Q01
Q21
Q41
Q40
/R
/W
A1
A3
A2
A4
A6
A5
A0
D11
D31
D30
D50
D61
D51
D10
D60
TKHKL
TKLKH
TKH/KH
T/KHKH
TKHKH
TCHQX1
TCHQV
TCHQX
TCHQX
TCHQZ
TDVKH
TKHDX
TDVKH
TKHDX
TKHKH
TIVKH
TKHIX
TAVKH
TKHAX
TAVKH
TKHAX
NOP
WRITE
CQ
/CQ
TCQHQV
TCHQV
TCHCQV
TCHCQX
TCHCQV
TKHCH
TCHCQX
Remarks 1.
Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2.
Outputs are disable (high impedance) one clock cycle after a NOP.
3.
In this example, if address A0=A1, data Q00=D10, Q01=D11.
Write data is forwarded immediately as read results.
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參數(shù)描述 |
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| UPD44325184BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325184BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
| UPD44325362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 1M x 36 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44325362F5-E40-EQ2 | 制造商:NEC Electronics Corporation 功能描述: |
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