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參數(shù)資料
| 型號： | UPD44325092F5-E50-EQ2 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的2字爆發(fā)運作 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 357K |
| 代理商： | UPD44325092F5-E50-EQ2 |
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11
Preliminary Data Sheet
M16783EJ1V0DS
μ
PD44325082, 44325092, 44325182, 44325362
Byte Write Operation
[
μ
PD44325082]
Operation
K
/K
/NW0
/NW1
Write D0 to D7
L
→
H
–
–
0
0
L
→
H
–
0
0
Write D0 to D3
L
→
H
–
0
1
L
→
H
–
0
1
Write D4 to D7
L
→
H
–
1
0
L
→
H
–
1
0
Write nothing
L
→
H
–
1
1
L
→
H
1
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /NW0 and /NW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
[
μ
PD44325092]
Operation
K
/K
/BW0
Write D0 to D8
L
→
H
–
–
0
L
→
H
–
0
Write nothing
L
→
H
–
1
L
→
H
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /BW0 can be altered for any portion of the BURST WRITE
operation provided that the setup and hold requirements are satisfied.
[
μ
PD44325182]
Operation
K
/K
/BW0
/BW1
Write D0 to D17
L
→
H
–
–
0
0
L
→
H
–
0
0
Write D0 to D8
L
→
H
–
0
1
L
→
H
–
0
1
Write D9 to D17
L
→
H
–
1
0
L
→
H
–
1
0
Write nothing
L
→
H
–
1
1
L
→
H
1
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /BW0 and /BW1 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
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PDF描述 |
|---|---|
| UPD44325182F5-E50-EQ2 | 36M-BIT QDRII SRAM 2-WORD BURST OPERATION |
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| UPD444004 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325094BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325094BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325182BF5-E33-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD44325182BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
| UPD44325182BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
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