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參數(shù)資料
| 型號： | UPD44325084F5-E50-EQ2-A |
| 元件分類： | SRAM |
| 英文描述： | 4M X 8 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 1/40頁 |
| 文件大?。?/td> | 387K |
| 代理商： | UPD44325084F5-E50-EQ2-A |
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MOS INTEGRATED CIRCUIT
μPD44325084, 44325094, 44325184, 44325364
36M-BIT QDRTM II SRAM
4-WORD BURST OPERATION
Document No. M16784EJ4V0DS00 (4th edition)
Date Published March 2007 NS CP(N)
Printed in Japan
DATA SHEET
2003
Description
The
μPD44325084 is a 4,194,304-word by 8-bit, the μPD44325094 is a 4,194,304-word by 9-bit, the μPD44325184 is a
2,097,152-word by 18-bit and the
μPD44325364 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μPD44325084, μPD44325094, μPD44325184 and μPD44325364 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and K#) are latched on the positive
edge of K and K#.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC BGA.
Features
1.8 ± 0.1 V power supply
165-pin PLASTIC BGA (13 x 15)
HSTL interface
PLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Four-tick burst for reduced address frequency
Two input clocks (K and K#) for precise DDR timing at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching-clock and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.
User programmable impedance output
Fast clock cycle time : 3.7 ns (270 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Operating ambient temperature: Commercial TA = 0 to +70°C
(-E37, -E40, -E50)
Industrial
TA = –40 to +85°C
(-E40Y, -E50Y)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325092BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44325094BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325094BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325182BF5-E33-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD44325182BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 2M x 18 0.45ns 165-Pin BGA 制造商:Renesas Electronics Corporation 功能描述:36MB, B2 QDRII SRAM - Trays |
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