
12
Preliminary Data Sheet
M16780EJ1V0DS
μ
PD44324082, 44324092, 44324182, 44324362
Bus Cycle State Diagram
READ DOUBLE
Count = Count + 2
WRITE DOUBLE
Count = Count + 2
Power UP
Write
NOP
Supply voltage provided
LOAD NEW
ADDRESS
Count = 0
NOP
Load, Count = 2
Read
Load, Count = 2
Load
NOP,
Count = 2
NOP,
Count = 2
Remarks 1.
A0 is internally advanced in accordance with the burst order table.
Bus cycle is terminated after burst count = 2.
2.
State machine control timing sequence is controlled by K.