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參數(shù)資料
| 型號： | UPD44164362BF5-E40-EQ3-A |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, LEAD FREE, PLASTIC, BGA-165 |
| 文件頁數(shù)： | 8/33頁 |
| 文件大?。?/td> | 494K |
| 代理商： | UPD44164362BF5-E40-EQ3-A |
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μPD44164182B-A, μPD44164362B-A
R10DS0014EJ0100 Rev.1.00
Page 16 of 32
Dec 13, 2010
Notes 1.
When debugging the system or board, these products can operate at a clock frequency slower than TKHKH
(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock
cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.
2.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var
(MAX.) indicates a peak-to-peak value.
3.
VDD slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention.
PLL lock time begins once VDD and input clock are stable.
It is recommended that the device is kept NOP (LD# = HIGH) during these cycles.
4. K input is monitored for this operation. See below for the timing.
K
TKC reset
or
TKC reset
5. Guaranteed by design.
6.
Echo clock is very tightly controlled to data valid / data hold. By design, there is a
± 0.1 ns variation from
echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.
7.
This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
Remarks 1. This parameter is sampled.
2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).
4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.
5. VDDQ is 1.5 V DC.
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相關(guān)代理商/技術(shù)參數(shù) |
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| UPD44164362F5-E60-EQ1ES | 制造商:NEC Electronics Corporation 功能描述: |
| UPD44165092BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:2MX9, 2BURST, 250 MHZ QDRII SRAM - Trays |
| UPD44165094BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 2M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44165362BF5-E40-EQ3 | 制造商:Renesas Electronics Corporation 功能描述:UPD44165362BF5-E40-EQ3 - Trays |
| UPD44165362BF5-E40-EQ3-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin BGA |
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