參數(shù)資料
型號(hào)： UPD3728DZ
廠商： NEC Corp.
英文描述： 7300 PIXELS x3 COLOR CCD LINEAR IMAGE SENSOR
中文描述： 7300像素X3的彩色CCD線性圖像傳感器
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 213K
代理商： UPD3728DZ
Data Sheet S15417EJ2V0DS
4
μ
PD3728DZ
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
25
°
C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
0.3 to
+
15
0.3 to
+
8
V
Shift register clock voltage
V
φ
1
, V
φ
1L
, V
φ
10
, V
φ
2
, V
φ
20
V
Reset gate clock voltage
V
φ
RB
0.3 to
+
8
V
Reset feed-through level clamp clock voltage
V
φ
CLB
0.3 to
+
8
V
Transfer gate clock voltage
V
φ
TG1
to V
φ
TG3
0.3 to
+
8
V
Operating ambient temperature
Note
T
A
25 to
+
60
°
C
Storage temperature
T
stg
40 to
+
100
°
C
Note
Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
25
°
C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
φ
1H
, V
φ
1LH
, V
φ
10H
, V
φ
2H
, V
φ
20H
4.5
5.0
5.5
V
Shift register clock low level
V
φ
1L
, V
φ
1LL
, V
φ
10L
, V
φ
2L
, V
φ
20L
0.3
0
+
0.5
V
Reset gate clock high level
V
φ
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
φ
RBL
0.3
0
+
0.5
V
Reset feed-through level clamp clock high level
V
φ
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock low level
V
φ
CLBL
0.3
0
+
0.5
V
Transfer gate clock high level
V
φ
TG1H
to V
φ
TG3H
4.5
V
φ
1H
Note
V
φ
1H
Note
V
(V
φ
10H
)
(V
φ
10H
)
Transfer gate clock low level
V
φ
TG1L
to V
φ
TG3L
0.3
0
+
0.5
V
Data rate
2f
φ
RB
2
40
MHz
Note
When Transfer gate clock high level (V
φ
TG1H
to V
φ
TG3H
) is higher than Shift register clock high level (V
φ
1H
(V
φ
10H
)), Image lag can increase.
Remark
Pin 9 (
φ
10) and pin 28 (
φ
20) should be open to decrease the influence of input clock noise to output
signal waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
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