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參數(shù)資料
| 型號(hào)： | UPD30500B |
| 廠商： | NEC Corp. |
| 英文描述： | VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR |
| 中文描述： | VR5000TM，VR5000ATM，VR5000BTM 64位微處理器 |
| 文件頁數(shù)： | 1/36頁 |
| 文件大?。?/td> | 210K |
| 代理商： | UPD30500B |
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1997,1999
DATA SHEET
1997
MIPS Technologies Inc.
MOS INTEGRATED CIRCUIT
μ
PD30500, 30500A, 30500B
Document No. U12031EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
DESCRIPTION
The
μ
PD30500 (V
R
5000),
μ
PD30500A (V
R
5000A), and
μ
PD30500B
Note
(V
R
5000B) are a high-performance, 64-
bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by
MIPS
TM
Technologies Inc.
The instructions of the V
R
5000, V
R
5000A, and V
R
5000B are compatible with those of the V
R
3000
TM
Series and
V
R
4000
TM
Series and higher, and completely compatible with those of the V
R
10000
TM
. Therefore, present
applications can be used as they are.
Note
Under development
Detailed functions are described in the following manual. Be sure to read the manual when
designing your system.
V
R
5000, V
R
5000A, V
R
5000B User’s Manual (U11761E)
FEATURES
Employs 64-bit MIPS-based RISC architecture
High-speed processing
2-way super scalar 5-stage pipeline
5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (
μ
PD30500)
6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (
μ
PD30500A)
8 SPECint95, 8 SPECfp95, 423 MIPS (
μ
PD30500B)
High-speed translation buffer mechanism (TLB) (48 entries)
Address space
Physical: 36 bits, Virtual: 40 bits
Floating-point unit (FPU)
Sum-of-products operation instruction supported
Primary cache memory (instruction/data: 32 Kbytes each)
Secondary cache controller
Maximum operating frequency Internal: 200 MHz (
μ
PD30500), 250 MHz (
μ
PD30500A), 300 MHz (
μ
PD30500B)
External: 100 MHz
Selectable external/internal multiple rate from twice to eight times
Instruction set compatible with V
R
3000 and V
R
4000 Series and higher (conforms to MIPS I, II, III, and IV)
Supply voltage: 3.3 V
±
5% (
μ
PD30500)
Core: 2.5 V
±
5%, I/O: 3.3 V
±
5% (
μ
PD30500A)
Core: 1.8 V
±
0.1 V, I/O: 3.3 V
±
5% (
μ
PD30500B)
Unless otherwise specified, the V
R
5000 (
μ
PD30500) is treated as the representative model throughout this
document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
V
R
5000
TM
, V
R
5000A
TM
, V
R
5000B
TM
64-BIT MICROPROCESSOR
The mark shows major revised points.
相關(guān)PDF資料 |
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| UPD30500S2-180 | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| UPD30500S2-200 | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| UPD3575 | 1024 BIT LINEAR IMAGE SENSOR |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD30500BS2-300 | 制造商:NEC 制造商全稱:NEC 功能描述:VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR |
| UPD30500RJ-150 | 制造商:NEC 制造商全稱:NEC 功能描述:VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR |
| UPD30500RJ-180 | 制造商:NEC 制造商全稱:NEC 功能描述:VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR |
| UPD30500RJ-200 | 制造商:NEC 制造商全稱:NEC 功能描述:VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR |
| UPD30500S2-150 | 制造商:NEC 制造商全稱:NEC 功能描述:VR5000TM, VR5000ATM, VR5000BTM 64-BIT MICROPROCESSOR |
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