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參數(shù)資料
| 型號： | UPD1724x |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLERS FOR SMALL GENERAL-PURPOSE INFRARED REMOTE CONTROL TRANSMITTERS |
| 中文描述： | 4位單片微控制器的小型通用兩用紅外遙控遞質(zhì) |
| 文件頁數(shù)： | 21/102頁 |
| 文件大?。?/td> | 461K |
| 代理商： | UPD1724X |
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21
Data Sheet U15002EJ1V0DS
μ
PD17240, 17241, 17242, 17243, 17244, 17245, 17246
2.3.2
Function of stack
The address stack register stores a return address when the subroutine call instruction or table reference
instruction (first instruction cycle) is executed or when an interrupt is acknowledged. It also stores the contents of
the address registers (ARs) when a stack manipulation instruction (PUSH AR) is executed.
If subroutines or interrupts are nested to more than 5 levels, the RESET pin is internally pulled down and
a reset is effected.
The interrupt stack register (INTSK) saves the contents of the bank register (BANK) and program status word
(PSWORD) when an interrupt is acknowledged. The saved contents are restored when an interrupt return (RETI)
instruction is executed.
INTSK saves data each time an interrupt is acknowledged, but
the data stored first is lost if more than 3 levels
of interrupts occur
.
2.3.3
Stack pointer (SP) and interrupt stack pointer
Table 2-3 shows the operations of the stack pointer (SP).
The stack pointer can take eight values, 0H to 7H. Because there are only five stack registers available, however,
the RESET pin is internally pulled down and reset is effected if the value of SP is 6 or greater
.
Table 2-3. Operations of Stack Pointer
Instruction
Value of Stack Pointer (SP)
Counter of Interrupt Stack Register
CALL addr
CALL @AR
MOVT DBF, @AR
(1st instruction cycle)
PUSH AR
SYSCAL entry
1
0
When interrupt is acknowledged
–
1
–
1
RET
RETSK
MOVT DBF, @AR
(2nd instruction cycle)
POP AR
+1
0
RETI
+1
+1
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