
60
μ
PD17145(A1), 17147(A1), 17149(A1)
17.3 STOP Mode
17.3.1 Setting STOP mode
The STOP mode is set when the STOP instruction is executed.
The operand of the STOP instruction, b
3
b
2
b
1
b
0
, specifies the condition under which the STOP mode is
released.
Table 17-4. STOP Mode Releasing Condition
Format: STOP b
3
b
2
b
1
b
0
B
Bit
STOP mode releasing condition
Note 1
b
3
Enables releasing HALT mode by IRQ
×××
when 1
Notes 2, 4
b
2
Fixed to “0”
b
1
Fixed to “0”
b
0
Enables releasing STOP mode by RLS input when 1
Notes 3, 4
Notes 1.
Only reset (RESET input or POC) is valid when STOP 0000B is specified. When STOP
0000B is executed, the internal circuitry of the microcontroller is initialized to the status
immediately after reset.
IP
×××
must be set to 1. The STOP mode cannot be released by IRQTM1.
b
0
alone cannot be set to 1 (STOP 0001B is prohibited).
Before setting b
0
to 1, be sure to set b
3
to 1.
Even if the STOP instruction is executed with IRQ
×××
= 1 or the RLS input being low, the
STOP instruction is ignored (treated as an NOP instruction), and the STOP mode is not set.
2.
3.
4.
17.3.2 Start address after STOP mode is released
The start address from which the program execution is started after the STOP mode has been released differs
depending on the condition under which the STOP mode has been released, and interrupt enable condition.
Table 17-5. Start Address after STOP Mode Is Released
Releasing Condition
Start Address after Release
Reset
Note 1
Address 0
RLS
Address next to that of STOP instruction
Address next to that of HALT instruction in DI status
IRQ
×××
Note 2
Interrupt vector in EI status
(if two or more IRQ
×××
flags are set, interrupt vector with higher priority)
Notes 1.
RESET input and POC are valid as reset.
IP
×××
must be set to 1. The STOP mode cannot be released by IRQTM1.
2.