μ
PD17072,17073
195
20.4.1 Power-ON clear voltage
The power-ON clear voltage differs as follows, depending on the CPU operating temperature range and operating
conditions:
T
A
= 0 to +70
°
C
T
A
= –10 to +70
°
C: 1.7 V MAX. (when CPU is operating and PLL frequency synthesizer and A/D converter stop)
T
A
= –20 to +70
°
C: 1.8 V MAX. (when CPU, PLL frequency synthesizer, and A/D converter are operating)
: 1.6 V MAX. (when CPU is operating and PLL frequency synthesizer and A/D converter stop)
The above values are the maximum values, and the actual power-ON clear voltage must be in a range that does
not exceed these maximum values.
The power-ON clear voltage during the CPU operation is the same as that in the clock stop status.
In the description below, the power-ON clear voltage is assumed to be 1.8 V.
20.4.2 Power-ON reset during normal operation
Figure 20-5 (a) shows the operation.
As shown in this figure, the power-ON clear signal is output regardless of the input level of the CE pin when the
supply voltage V
DD
drops below 1.8 V (T
A
= –20 to +70
°
C, when CPU, PLL, A/D are operating), and the device operation
is stopped.
When the supply voltage V
DD
rises beyond 1.8 V again, the program starts from address 0000H after a halt status
of 125 ms or more.
The CPU operation includes when the clock stop instruction is not used, and power-ON clear voltage is 1.8 V during
halt status set by the halt instruction.
20.4.3 Power-ON reset in clock stop mode
Figure 20-5 (b) shows the operation.
As shown in this figure, the power-ON clear signal is output and the device operation is stopped when the supply
voltage V
DD
drops below 1.7 V (T
A
= –20 to +70
°
C, when CPU, PLL, A/D are operating).
However, because the clock stop mode is set, the operation of the device seems not to be changed.
When the supply voltage V
DD
rises beyond 1.8 V, the program starts from address 0000H after a halt of 125 ms
or more.
20.4.4 Power-ON reset when supply voltage V
DD
rises from 0 V
Figure 20-5 (c) shows the operation.
As shown in this figure, the power-ON clear signal is output until the supply voltage V
DD
rises from 0 V to 1.8 V
(T
A
= –20 to +70
°
C, CPU, PLL, A/D are operating).
When the supply voltage V
DD
exceeds the power-ON clear voltage, the crystal oscillator circuit starts operating,
and the program starts from address 0000H after a halt of 125 ms or more.