參數(shù)資料
型號(hào)： UPD17006AGF-011-3B9
廠商： NEC Corp.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No
中文描述： 4位單片機(jī)帶預(yù)分頻器的微控制器，鎖相環(huán)頻率合成器，如果汽車調(diào)頻，兆瓦，和LW收音機(jī)計(jì)數(shù)器
文件頁數(shù)： 68/72頁
文件大?。?/td> 677K
代理商： UPD17006AGF-011-3B9
68
μ
PD17006AGF-011
I
OL4
Parameter
Symbol
Unit
MIN.
TYP.
MAX.
DC Characteristics (T
a
= –40 to +85
°
C, V
DD
= 5 V
±
10 %)
I
DD1
15.0
22.0
mA
I
DD2
3.5
9.0
mA
I
DD3
17.0
mA
I
DD4
V
DDR1
5.5
V
4.1
Supply Current
0.5
1.2
mA
Condition
When CPU and PLL operate
VCOH pin: 150 MHz, 0.3 V
p-p
input
X
IN
pin sine wave input (f
IN
= 4.5 MHz, V
IN
= V
DD
)
When CPU operates and PLL is stopped
X
IN
pin sine wave input (f
IN
= 4.5 MHz, V
IN
= V
DD
)
When CPU and PLL operate, and HALT
instruction is used
VCOH pin: 150 MHz, 0.3 V
p-p
input
(without HALT release condition)
X
IN
pin sine wave input (f
IN
= 4.5 MHz, V
IN
= V
DD
)
When CPU operates, PLL is stopped, and
HALT instruction is used
(20 instructions executed every 1 ms)
X
IN
pin sine wave input (f
IN
= 4.5 MHz, V
IN
= V
DD
)
When crystal oscillates and power fail-
ure detection by timer FF is used
When crystal oscillation stopped and
power failure detection by timer FF is
used
Data memory retention
When crystal
oscillation is
stopped
V
DD
= 5 V, T
a
= 25
°
C
P0A
0
, P0A
3
, P0B
0
, P0B
1
, P0B
3
, P0C
0
-P0C
3
,
P2A
0
-P2A
3
, P2B
0
-P2B
3
, P2C
0
-P2C
3
,
P2D
0
-P2D
3
, P3A
0
-P3A
3
, P3B
0
-P3B
3
CE, INT
0
, INT
1
, P0A
2
/SCL, P0A
1
/SCK
0
,
P0B
2
/SCK
1
P0D
0
/P0D
3
P0A
0
-P0A
3
, P0B
0
-P0B
3
, P0C
0
-P0C
3
,
P0D
0
-P0D
3
, P2A
0
-P2A
3
, P2B
0
-P2B
3
,
P2C
0
-P2C
3
, P2D
0
-P2D
3
, P3A
0
-P3A
3,
P3B
0
-P3B
3
, CE, INT
0
, INT
1
P0A
0
, P0A
1
, P0B
0
-P0B
3
, P0C
0
-P0C
3
,
P1A
0
-P1A
3
, P1B
0
, P1C
2
, P2A
0
-P2A
3
,
P2B
0
-P2B
3
, P2C
0
-P2C
3
, P2D
0
-P2D
3,
P3A
0
-P3A
3
, P3B
0
-P3B
3
, P3C
0
-P3C
3
, P3D
3
,
P4A
2
, P4A
3
V
OH
= V
DD
–1V
EO
0
, EO
1
V
OH
= V
DD
–1V
P0A
0
, P0A
1
, P0B
0
-P0B
3
, P0C
0
-P0C
3
,
P1A
0
-P1A
3
, P1B
0
, P1C
2
, P2A
0
-P2A
3
,
P2B
0
-P2B
3
, P2C
0
-P2C
3
, P2D
0
-P2D
3,
P3A
0
-P3A
3
, P3B
0
-P3B
3
, P3C
0
-P3C
3
, P3D
3
,
P4A
2
, P4A
3
V
OL
= 1V
EO
0
, EO
1
V
OL
= 1V
P1B
1
, P1B
3
V
OL
= 1V
P0A
2
, P0A
3
V
OL
= 1V
V
DDR3
I
DDR1
I
DDR2
5.5
2.0
V
μ
A
5
2
μ
A
20
2
0.7 V
DD
V
V
IH1
V
IH2
0.8 V
DD
V
V
IH3
0.6 V
DD
V
V
IL
0.2 V
DD
V
I
OH1
mA
–1.0
–2.0
I
OH2
mA
–1.0
–3.0
I
OL1
mA
1.0
2.0
I
OL2
mA
1.0
3.0
I
OL3
mA
1.0
2.0
mA
1.0
10.0
Low-Level Input
Voltage
Data Retention Current
High-Level Input Voltage
High-Level Output Current
Low-Level Output Current
Data Retention Voltage
V
DDR2
5.5
V
2.3
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