參數(shù)資料
型號(hào): UPD16754
英文描述: UPD16754 Data Sheet | Data Sheet[04/2003]
中文描述: UPD16754數(shù)據(jù)表|數(shù)據(jù)表[04/2003]
文件頁(yè)數(shù): 5/20頁(yè)
文件大?。?/td> 157K
代理商: UPD16754
Data Sheet S15859EJ1V0DS
5
μ
PD160040
(2/2)
Pin Symbol
Pin Name
I/O
Description
MODE
Output reset control
Input
MODE = H or open: Output reset
MODE = L: No output reset
MODE is pulled up to the V
DD1
in the IC.
POL21,
POL22
Data inversion
Input
Select of inversion or no inversion for input data.
POL21: Data inversion or no inversion of Port1.
POL22: Data inversion or no inversion of Port2
POL21, POL22 = H: Data are inverted in the IC.
POL21, POL22 = L: Data are not inverted in the IC.
V
SEL
Driver voltage select
Input
The driver voltage can be switched by controlling the stationary bias
current of the output amplifier via V
SEL
.
V
SEL
= H: V
DD2
= 12.5 to (14.0 V) (large bias current)
V
SEL
= L or open: V
DD2
= (14.0 V) to 15.0 V (small bias current)
LPC is pulled down to the V
SS1
in the IC.
TEST
Test
Input
Normally, set the TEST pin to H or leave open.
This pin is pulled up to V
DD1
in the IC.
Input the
γ
-corrected power supplies from outside by using operational
amplifier. During the gray scale voltage output, be sure to keep the gray
scale level power supply at a constant level. Make sure to maintain the
following relationships.
V
DD2
– 0.2 V
V
0
> V
1
> V
2
> V
1
> V
2
>... ... > V
6
> V
7
0.5 V
DD2
+ 0.5 V
0.5 V
DD2
– 0.5 V
V
8
>
V
9
> V
10
> ... ... > V
14
> V
15
V
SS2
+ 0.2 V
2.5 to 3.6 V
V
0
-V
15
γ
-corrected power supplies
V
DD1
Logic power supply
V
DD2
Driver power supply
12.5 to 15.5 V
V
SS1
Logic ground
Grounding
V
SS2
Driver ground
Grounding
Cautions 1. The power start sequence must be V
DD1
, logic input, and V
DD2
& V
0
-V
15
in that order.
Reverse this sequence to shut down.
2. To stabilize the supply voltage, please be sure to insert a 0.47
μ
F bypass capacitor between
V
DD1
-V
SS1
and V
DD2
-V
SS2
. Furthermore, for increased precision of the D/A converter,
insertion of a bypass capacitor of about 0.1
μ
F is also advised between the
γ
-corrected
power supply terminals (V
0
, V
1
, V
2
,.. ..., V
15
) and V
SS2
.
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