參數(shù)資料
型號(hào)： UPD16750
廠商： NEC Corp.
英文描述： 384-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 256-GRAY SCALES
中文描述： 384輸出的TFT - LCD源驅(qū)動(dòng)程序完全兼容256灰度
文件頁(yè)數(shù)： 4/24頁(yè)
文件大?。?/td> 188K
代理商： UPD16750
Data Sheet S13719EJ4V0DS00
4
μ
PD16750
4. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
S
1
to S
384
Driver output
The D/A converted 256-gray-scale analog voltage is output.
D
00
to D
07
D
10
to D
17
D
20
to D
27
D
30
to D
37
D
40
to D
47
D
50
to D
57
Display data input
The display data is input with a width of 48 bits, viz., the gray scale data (8 bits) by 6 dots (2
pixels).
D
X0
: LSB, D
X7
: MSB
R,/L
Shift direction control
input
These refer to the start pulse input/output pins when driver ICs are connected in cascade.
The shift directions of the shift registers are as follows.
R,/L = H
: STHR input, S
1
→
S
384
, STHL output
: STHL input, S
384
→
S
1
, STHR output
R,/L = L
STHR
Right shift start pulse
input/output
R,/L = H
: Becomes the start pulse input pin.
R,/L = L
: Becomes the start pulse output pin.
STHL
Left shift start pulse
input/output
R,/L = H
: Becomes the start pulse output pin.
R,/L = L
: Becomes the start pulse input pin.
CLK
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge of the 64th clock after the start pulse input, the start pulse output
reaches the high level, thus becoming the start pulse of the next-level driver.
STB
Latch input
The contents of the data register are transferred to the latch circuit at the rising edge. And,
at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure
input of one pulse per horizontal period.
POL
Polarity input
POL = L
: The S
2n–1
output uses V
0
to V
7
as the reference supply. The S
2n
output uses V
8
to V
15
as the reference supply.
POL = H : The S
2n–1
output uses V
8
to V
15
as the reference supply. The S
2n
output uses V
0
to V
7
as the reference supply.
S
2n-1
indicates the odd output: and S
2n
indicates the even output. Input of the POL signal is
allowed the setup time(t
POL
-
STB
) with respect to STB’s rising edge.
POL21
POL22
Data inversion
Data inversion can invert when display data is loaded.
POL21/22 = H : Data inversion loads display data after inverting it.
POL21/22 = L : Data inversion does not invert input data.
POL21: D
00
to D
07
, D
10
to D
17
, D
20
to D
27
POL22: D
30
to D
37
, D
40
to D
47
, D
50
to D
57
LPC
Low power control
input
The output buffer constant current source is blocked, reducing current consumption. In lower
power mode (LPC = L: DC-level input possible), the ordinary static current consumption can
be reduced by approx. 33 %.
V
0
to V
15
γ
-corrected power
supplies
Input the
γ
-corrected power supplies from outside by using operational amplifier. Make sure
to maintain the following relationships. During the gray scale voltage output, be sure to keep
the gray scale level power supply at a constant level.
V
DD2
0.2 V > V
0
> V
1
> V
2
> V
3
> V
4
> V
5
> V
6
> V
7
> 0.5 V
DD2
0.5 V
DD2
0.3 V > V
8
> V
9
> V
10
> V
11
> V
12
> V
13
> V
14
> V
15
> V
SS2
+ 0.2 V
V
DD1
Logic power supply
3.3 V
±
0.3 V
V
DD2
Driver power supply
9.0 V
±
0.5 V
V
SS1
Logic ground
Grounding
V
SS2
Driver ground
Grounding
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UPD16750N 制造商:NEC 制造商全稱:NEC 功能描述:384-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 256-GRAY SCALES
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