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參數(shù)資料
| 型號： | UPD16732BN-XXX |
| 廠商： | NEC Corp. |
| 英文描述： | LCD Display Driver |
| 中文描述： | 液晶顯示驅(qū)動程序 |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 186K |
| 代理商： | UPD16732BN-XXX |
1999
MOS INTEGRATED CIRCUIT
μ
PD16732A, 16732B
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
Document No. S13972EJ3V0DS00 (3rd edition)
Date Published August 1999 NS CP(K)
Printed in Japan
DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark
#
shows major revised points.
DESCRIPTION
The
μ
PD16732A, 16732B are a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales.
Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of
260,000 colors by output of 64 values
γ
-corrected by an internal D/A converter and 5-by-2 external power modules.
Because the output dynamic range is as large as V
SS2
+ 0.1 V to V
DD2
– 0.1 V, level inversion operation of the LCD’s
common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and
column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter
circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity.
Assuring a maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is
applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels by input display signal 2 systems (Clock
divide).
FEATURES
CMOS level input (2.3 V to 3.6 V)
384 Outputs
Input of 6 bits (gradation data) by 6 dots
Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and
a D/A converter (R-DAC)
High-speed data transfer: f
MAX.
= 65 MHz (internal data transfer speed when operating at V
DD1
=
3.0 V)
Output dynamic range V
SS2
+ 0.1 V to V
DD2
– 0.1 V
Apply for dot-line inversion, n-line inversion and column line inversion
Output Voltage polarity inversion function (POL)
Display data inversion function (POL2)
Low power control function (LPC)
Logic power supply voltage (V
DD1
) : 2.3 V to 3.6 V
Driver power supply voltage (V
DD2
) : 8.5
±
0.5 V
Different point between
μ
PD16732A, 16732B : The ladder resistors value(Refer to
5. RELATIONSHIP
BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
)
ORDERING INFORMATION
Part Number Package
μ
PD16732AN-
×××
TCP (TAB package)
μ
PD16732BN-
×××
TCP (TAB package)
Remark
The TCP’s external shape is customized. To order the required shape, please contact an NEC
salesperson.
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| UPD16750N-XXX | LCD Display Driver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD16732D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16732D Data Sheet | Data Sheet[06/2002] |
| UPD16732E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UPD16732E Data Sheet | Data Sheet[06/2002] |
| UPD16732N-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
| UPD16738N-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC |
| UPD16740N-XXX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
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