參數(shù)資料
型號: UPD16662
廠商: NEC Corp.
英文描述: 240 OUTPUT LCD COLUMN SEGMENT DRIVER WITH BUILT-IN RAM
中文描述: 240輸出LCD列段驅(qū)動,配有內(nèi)存
文件頁數(shù): 26/36頁
文件大小: 260K
代理商: UPD16662
26
μ
PD16662
5. AC Characteristics 2 Graphic Access Timing
(Unless otherwise specified, V
CC1
= 4.5 to 5.5 V, V
CC2
= 3.0 to 3.6 V. V
0
= 0 V, V
1
= 1.4 to 2.0 V, V
2
= 2.8 to 4.0 V,
T
A
=
20 to +70
°
C, t
r
= t
f
= 5 ns)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Remark
Notes
/OE, /WE recovery time
t
RY
30
ns
Address setup time
t
AS
10
ns
Address hold time
t
AH
20
ns
RDY output delay time
t
RYR
30
ns
CL = 15 pF
RDY float time
t
RYZ
30
ns
3
Wait state time
t
RYW
35
ns
1
Ready state time (without contention)
t
RYF1
60
100
ns
1
Ready state time (with contention)
t
RYF2
650
1,200
ns
1
Data access time (Read cycle)
t
ACS
100
ns
2
Data float time (Read cycle)
t
HZ
40
ns
3
/CS - /OE time (Read cycle)
t
CSOE
10
ns
/OE - /CS time (Read cycle)
t
OECS
20
ns
Write pulse width 1 (Write cycle 1)
t
WP1
50
ns
1
Write pulse width 2 (Write cycle 2)
t
WP2
50
ns
1
Data setup time (Write cycle 1, 2)
t
DW
20
ns
Data hold time (Write cycle 1, 2)
t
DH
20
ns
/CS - /WE time (Write cycle 1, 2)
t
CSWE
10
ns
/WE - /CS time (Write cycle 1, 2)
t
WECS
20
ns
Reset pulse width
t
WRES
100
ns
RDY - /OE time
t
RDOE
4
RDY - /WE time
t
RDWE
4
Notes 1.
Load circuit
V
CC2
1.8 k
60 pF
1.0 k
2.
Load circuit
V
CC2
1.8 k
100 pF
1.0 k
3.
Load circuit
V
CC2
1.8 k
5 pF
1.0 k
4.
The display may be affected if the time from the rising of RDY to /OE or /WE is too long. It is recommended
that t
RDOE
and t
RDWE
be 1,000 ns MAX.
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