參數(shù)資料
型號(hào)： UPD16638N
英文描述： LCD Display Driver
中文描述： 液晶顯示驅(qū)動(dòng)程序
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 157K
代理商： UPD16638N
Data Sheet S15859EJ1V0DS
14
μ
PD160040
Electrical Characteristics (T
A
= –10 to +75
°
C, V
DD1
= 2.5 to 3.6 V, V
DD2
= 12.5 to 15.5 V, V
SS1
= V
SS2
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input leakage current
I
IL
±
1.0
μ
A
V
High-level output voltage
V
OH
STHR (STHL), I
OH
= 0 mA
V
DD1
0.1
Low-level output voltage
γ
-corrected resistance
Driver output current
V
OL
STHR (STHL), I
OL
= 0 mA
0.1
V
k
mA
R
γ
V
DD2
= 15.0 V, V
0
-V
7
= V
8
-V
15
= 7.0 V
V
X
= 12.0 V, V
OUT
= 11.0 V
Note1
V
X
= 1.0 V, V
OUT
= 2.0 V
Note1
5.14
10.3
15.4
0.40
I
VOH
I
VOL
V
O
V
P-P1
V
P-P2
V
P-P3
I
DD1
0.65
mA
Output voltage deviation
T
A
= 25
°
C, V
SS2
+ 1.0 V to V
DD2
1.0 V
V
OUT
= 7.0 to 8.0 V
Note1
V
OUT
= 4.0 to 11.0 V
Note1
V
DD2
= 15.0 V,
T
A
= 25
°
C
V
OUT
= 1.0 to 14.0 V
Note1
V
DD1
Notes2,3
±
10
±
5
±
7
±
10
1.3
±
20
±
10
±
15
±
20
12
mV
mV
mV
Output swing voltage difference
deviation
V
DD1
= 3.3 V,
mV
Logic part dynamic current
consumption
mA
Driver part dynamic current
consumption
I
DD2
V
DD2
, with no load
Notes3,4
12
30
mA
Notes 1.
V
X
refers to the output voltage of analog output pins S
1
to
S
384
.
V
OUT
refers to the voltage applied to analog output pins S
1
to S
384
2.
f
STB
= 64 kHz, f
CLK
= 54 MHz
3.
The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured
values in the dot checkerboard input pattern.
4.
Refers to the current consumption per driver when cascades are connected under the assumption of SXGA
single-sided mounting (10 units).
Switching Characteristics (T
A
=
10 to +75
°
C, V
DD1
= 2.5 to 3.6 V, V
DD2
= 12.5 to 15.5 V, V
SS1
= V
SS2
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
C
L
= 15 pF, 3.0 V
≤
V
DD
≤
3.6 V
C
L
= 15 pF, 2.5 V
≤
V
DD
< 3.0 V
C
L
= 100 pF, R
L
= 10 k
17
ns
Start pulse delay time
t
PLH1
24
ns
μ
s
μ
s
μ
s
μ
s
pF
Driver output delay time
t
PLH2
Note
t
PLH3
Note
t
PHL2
Note
t
PHL3
Note
5
10
5
10
Input capacitance
C
I1
logic input, except STHR (STHL),
T
A
= 25
°
C
STHR (STHL), T
A
= 25
°
C
5
10
C
I2
10
15
pF
Note
t
PLH2
,
t
PHL2
refer to the arrival time from falling edge of STB to target voltage
±
10%
t
PLH3
,
t
PHL3
refer to the
arrival time from falling edge of STB to target voltage
±
0.02 V (condition: V
O
= 3.0 V
12.0 V)
<Test Condition>
C
L1
C
L2
C
L3
R
L3
R
L2
R
L5
R
Ln
= 2 k
C
Ln
= 20 pF
C
L4
R
L4
C
L5
R
L1
Output
Measurement
point
GND
#
#
#
#
#
#
#
#
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