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參數(shù)資料
| 型號： | UPD16406N001 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 157K |
| 代理商： | UPD16406N001 |
Data Sheet S15859EJ1V0DS
11
μ
PD160040
7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND OUTPUT WAVEFORM
When MODE = H or open and STB = H, all outputs are reset (short) and the gray-scale voltage is output to LCD in
synchronization with the falling edge of STB.
When MODE = L and STB = H, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in
synchronization with the falling edge of STB.
Also, setting the SRC pin to H level allows the bias current value of the output amplifier to rise temporarily, and
setting the ORC pin to H level allows the output resistance value of the amplifier to lower temporarily.
For the timing and the processing of STB, SRC, or ORC during a high-level period, We recommend a thorough
evaluation of the LCD panel specifications in advance.
(1) MODE = H or open
STB
POL
S
2n
–
1
S
2n
Hi-Z
Hi-Z
Hi-Z
SRC
ORC
Low through rate period
High output resistance period
Voltage selected form V
0
to V
7
Voltage selected form V
0
to V
7
Voltage selected form V
8
to V
15
Voltage selected form V
0
to V
7
Voltage selected form V
8
to V
15
High through rate period
Voltage selected form V
8
to V
15
Low output resistance period
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