參數(shù)資料
型號: UPC1854A
廠商: NEC Corp.
英文描述: I2C BUS-COMPATIBLE US MTS PROCESSING LSI
中文描述: I2C總線兼容美國的多邊貿(mào)易體制處理LSI
文件頁數(shù): 30/48頁
文件大小: 251K
代理商: UPC1854A
μ
PC1854A
30
Data Sheet S12816EJ3V0DS00
5. MODE MATRIX
5.1 L-, R-Channel Output (LOT, ROT pins) Matrix
Mute OFF (Write register, subaddress 06H, bit D0 : “1”)
(1) Read register, bit D4: 0
Broadcast
mode
Write Register
Output
Read Register
Forced
monaural
ON/OFF
Stereo/SAPSAP1/SAP2
switch
Stereo/SAP
output stop
L-ch
output
(LOT)
R-ch
output
(ROT)
Broadcast status
Reception status
switch
Stereo
pilot
SAP
signal
Stereo
broadcast broadcast
reception
SAP
Subaddress 06H
Subaddress 00H
reception
Bit D1
Bit D2
Bit D3
Bit D6
Bit D6
Bit D5
Bit D3
Bit D2
Monaural
L+R
0
0
0
0
Stereo
0
L
R
1
0
1
0
1
L+R
0
Monaural
+ SAP
0
0
L+R
0
1
0
0
1
0
SAP
1
1
L+R
SAP
1
L+R
0
Stereo + SAP
0
0
L
R
1
1
1
0
1
0
SAP
0
1
1
L+R
SAP
1
L+R
0
(2) Read register, bit D4: 1
Broadcast
mode
Write Register
Output
Read Register
Forced
monaural
ON/OFF
Stereo/SAPSAP1/SAP2
switch
Stereo/SAP
output stop
L-ch
output
(LOT)
R-ch
output
(ROT)
Broadcast status
Reception status
switch
Stereo
pilot
SAP
signal
Stereo
broadcast broadcast
reception
SAP
Subaddress 06H
Subaddress 00H
reception
Bit D1
Bit D2
Bit D3
Bit D6
Bit D6
Bit D5
Bit D3
Bit D2
Monaural
L+R
0
0
0
0
Stereo
0
0
L
R
1
0
1
0
1
L+R
0
0
Monaural
+ SAP
0
1
0
0
L+R
0
0
0
0
1
1
0
1
Stereo + SAP
0
0
0
L
R
1
0
1
0
1
L+R
0
0
1
0
0
1
1
0
1
Remarks 1.
When the
μ
PC1854A recognizes a weak electric field, bit D4 of the read register becomes “1”.
2.
— : Don’t care.
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