
53
μ
PC1851B
Data Sheet S13417EJ2V0DS00
(6/8)
Parameter
Symbol
Test Conditions
User Mode
Note
Inter-mode DC offset 2
V
DOF2
V
DOF2
= V
ST
– V
Mute
V
ST
: DC voltage at LOT and ROT pins
User mode : Stereo
NDT pin: 6 V DC is applied.
V
Mute
: DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Mute
to
Stereo
Inter-mode DC offset 3
V
DOF3
V
DOF3
= V
SAP
– V
Mute
V
SAP
: DC voltage at LOT and ROT pins
User mode : SAP1
NDT pin: 6 V DC is applied.
V
Mute
: DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Mute
to
SAP1
Inter-mode DC offset 4
V
DOF4
V
DOF4
= V
MONO
– V
Mute
V
MONO
: DC voltage at LOT and ROT pins
User mode : External input
NDT pin: 6 V DC is applied.
V
Mute
: DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Mute
to
External
input
Surround output
characteristics 1
V
SR1L
V
SR1L
= 20 log (V
L1
÷
V
EL
)
V
L1
: Output voltage of LOT pin
V
EL
: Input voltage of EL1, EL2 pins (100 Hz, 150 mV
rms
)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
External input 1
External input 2
Surround output
characteristics 2
V
SR2L
V
SR2L
: 20 log (V
L2
÷
V
EL
)
V
L2
: Output voltage of LOT pin
V
EL
: Input voltage of EL1, EL2 pins (1 kHz, 150 mV
rms
)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
characteristics 3
V
SR3L
V
SR3L
: 20 log (V
L3
÷
V
EL
)
V
L3
: Output voltage of LOT pin
V
EL
: Input voltage of EL1, EL2 pins (10 kHz, 150 mV
rms
)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
characteristics 4
V
SR4R
V
SR4R
: 20 log (V
R
÷
V
EL
)
V
R
: Output voltage of ROT pin
V
EL
: Input voltage of EL1, EL2 pins (1 kHz, 150 mV
rms
)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Note
For details about the User Mode, refer to
5. MODE MATRIX
.