
PART NUMBER
PACKAGE OUTLINE
PARAMETERS AND CONDITIONS
UPB1007K
QFN-36
TYP
SYMBOLS
UNITS
MIN
MAX
I
CC
Total Circuit Current, No Signals
mA
25
31
V
CC
Supply Voltage
V
2.7
3.0
3.3
LNA (f
RFin
= 1575.42 MHz, Z
L
= Z
S
= 50
)
Z
LNAin
Z
LNAop
P
1dBLNA
PG
LNA
NF
LNA
Mixer (f
RFin
= 1575.42 MHz, f
1stLOin
= 1636.80 MHz, P
LO
= -10 dBm, f
1stIF
= 61.38 MHz, Z
L
= Z
S
= 50
)
Z
MIXin
RF Input Impedance of Mixer
P
1dBMIX
1 dB Compression (refer to input), Input matched
PCG
MIX
Power Conversion Gain
NF
MIX
Noise Figure of Mixer (SSB), Input matched
A
LO-IF
LO Leakage to IF Pins, P
LO
= -10 dBm
A
LO-RF
LO Leakage to RF Input Pins, P
LO
= -10 dBm
Z
MIXout
RF Output Impedance of Mixer
PLL
I
CPOH
PLL Charge Pump High Side Current @ V
CPout
= V
CC/
2
I
CPOL
PLL Charge Pump Low Side Current @ V
CPout
= V
CC/
2
f
PD
Phase Comparison Frequency
IF Downconverter Block (f
1stIFin
= 61.38 MHz, f
2ndLOin
= 65.472 MHz, f
2ndIF
output = 4.092 MHz, Z
S
= 2k
, Z
L
= 2 k
)
NF
2ndMIX
Noise Figure of 2nd IF Mixer (SSB), (Z
S
= 50
)
GV
2ndMIX
Voltage Gain of 2nd Mixer/Amplifier, P
1stIF
= -50 dBm
V
GC
Gain Control Voltage (Voltage at maximum gain)
D
GC
Gain Control Range, P
1stIF
= -50 dBm
(Voltage at maximum gain)
A
2ndLO1stIF
2nd LO Isolation to 1st IF Input Pins, V
AGC
= 0 V
A
2ndLO2ndIF
2nd LO Isolation to 2nd IF Output Pins, V
AGC
= 0 V
RF Input Impedance of LNA
RF Output Impedance of LNA
1 dB Compression, Input matched
Power Gain LNA, Input matched, P
RFin
= -60 dBm
Noise Figure of LNA, Input matched
28 - j38
85 - jx6
-22
15
2.8
dBm
dB
dB
14
3.2
31 -j103
-25
21
9.5
-40
-48
+152 - j9
dBm
dB
dB
dBm
dBm
10
mA
mA
MHz
1
-1
8.184
dB
dB
V
dB
12
47
0.5
20
dB
dB
-70
-70
FEATURES
UPB1007K
NEC's 3 V DUAL
DOWNCONVERTER AND
PLL FREQUENCY SYNTHESIZER
DESCRIPTION
NEC's UPB1007K is a Silicon RFIC designed for low cost GPS
receivers. The IC combines an LNA, followed by a double-
conversion RF/IF downconverter block and a PLL frequency
synthesizer on one chip. The device operates on a 3V supply
voltage and is housed in a small 36 pin QFN (Quad Flat No-
lead) package, resulting in low power consumption and re-
duced board space. The device is manufactured using the
state of the art UHS0 25 GHz f
T
silicon bipolar process.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and performance.
ELECTRICAL CHARACTERISTICS
(T
A
= 25
°
C, V
CC
= 3.0 V, unless otherwise specified)
APPLICATIONS
LOW POWER HANDHELD GPS RECEIVER
IN-VEHICLE NAVIGATION SYSTEMS
PC/PDA+GPS INTEGRATION
INTEGRATED RF BLOCK:
LNA, RF & IF Downconverter + PLL frequency
synthesizer
STATE OF THE ART 25 GHz f
T
UHS0 BIPOLAR
PROCESS
DOUBLE-CONVERSION:
f
1stIF
= 61.380 MHz
f
2ndIF
= 4.092 MHz
ADJUSTABLE GAIN:
20 dB range MIN
FIXED DIVISION PRESCALER
LOW POWER CONSUMPTION:
25 mA @ 3 V
SMALL 36 PIN QFN PACKAGE
Flat lead style for better performance
TAPE AND REEL PACKAGING AVAILABLE
California Eastern Laboratories