參數(shù)資料
型號: UMA1021M
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: Low-voltage frequency synthesizer for radio telephones
中文描述: PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO20
封裝: 4.40 MM, PLASTIC, SOT-266-1, SSOP-20
文件頁數(shù): 10/16頁
文件大?。?/td> 107K
代理商: UMA1021M
1999 Jun 17
10
Philips Semiconductors
Product specification
Low-voltage frequency synthesizer
for radio telephones
UMA1021M
SERIAL BUS TIMING CHARACTERISTICS
V
DD
= V
CC
= 3 V; T
amb
= 25
°
C; unless otherwise specified.
Note
1.
The minimum pulse width (t
W(min)
) can be smaller than 4
μ
s provided all the following conditions are fulfilled:
a) Main divider input frequency
.
b) Reference divider input frequency
.
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
t
r
t
f
T
cy
input rise time
input fall time
clock period
100
10
10
40
40
ns
ns
ns
Enable programming; E
t
START
t
END
t
W(min)
t
SU;E
delay to rising clock edge
delay from last falling clock edge
minimum inactive pulse width
enable set-up time to next clock edge
40
20
4000
(1)
20
ns
ns
ns
ns
Register serial input data; DATA
t
SU;DAT
t
HD;DAT
input data to clock set-up time
input data to clock hold time
20
20
ns
ns
f
RF
t
W min
)
---447
>
f
xtal
W min
)
t
>
Fig.3 Serial bus timing diagram.
handbook, full pagewidth
MGD565
MSB
LSB
ADDRESS
tSTART
tHD;DAT
Tcy
tr
tf
tW(min)
tENDtSU;E
CLK
DATA
E
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