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參數(shù)資料
| 型號： | UMA1016BT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Frequency synthesizer for radio communication equipment |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 800 MHz, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012AC, SOT-109-1, SOP-16 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 85K |
| 代理商： | UMA1016BT |
1995 Jul 12
4
Philips Semiconductors
Product specification
Frequency synthesizer for
radio communication equipment
UMA1016xT
PINNING
SYMBOL
PIN
DESCRIPTION
RO1
1
crystal oscillator input or TCXO
input
oscillator output to crystal circuit
5 V supply to digital section
reference crystal frequency
buffered output
Hardware Power-Down Not;
IC operates when pin is HIGH
digital ground
1 GHz RF signal input
internally connected
programming bus data input
programming bus clock input
programming bus enable input
(active LOW)
transmit (HIGH)/receive (LOW)
mode select input
internally connected
analog ground
5 V supply to charge pump
circuit
charge pump output
RO2
V
DD
REFCK
2
3
4
HPDN
5
DGND
RFI
i.c.
DATA
CK
EN
6
7
8
9
10
11
TX/RX
12
i.c.
AGND
V
CC
13
14
15
CP
16
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
VCC
AGND
i.c.
TX/RX
EN
CK
DATA
RO1
RO2
VDD
REFCK
HPDN
DGND
RFI
i.c.
UMA1016XT
MGA192 - 1
FUNCTIONAL DESCRIPTION
General
The UMA1016xT is a low power synthesizer for radio
communications in the range 500 to 1000 MHz. It includes
an oscillator circuit, reference divider, RF divider, 3-state
phase and frequency comparator, charge pump and main
control circuit for the transfer of serial data into two internal
registers.
V
DD
supplies power to the digital circuits while V
CC
powers
the charge pump. V
DD
and V
CC
are nominally 5 V but will
operate in the range 4.5 V to 5.5 V.
Reduced noise coupling is facilitated by separate digital
and analog ground pins which must always be externally
connected to the same DC potential to prevent the flow of
large currents across the die.
The synthesizer is placed in idle mode during power-down
but the oscillator and buffer remain operative and may be
used as a clock for system timing.
Main divider
The main divider is a fully programmable pulse-swallow
type. Following a sensitive (50 mV,
13 dBm) input
amplifier, the RF signal is applied to a 13-bit divider
(MD13 to MD1). The division ratio is provided via the serial
bus to two 13-bit latches, corresponding to transmit and
receive frequencies. The serial programming register is
written to under processor control, independently of divider
operation. This removes difficulty if using a low data bus
transmission speed. The new ratio is transferred to the
appropriate latch when the programming enable signal
(EN) returns HIGH.
The last register bit (PB0) is used to determine whether the
new value is loaded into the transmit (PB0 = 1) or receive
(PB0 = 0) frequency latch. To avoid spurious phase
changes, the divider incorporates the new ratio only at the
end of the on-going reference period. The minimum
division ratio is 512. One reference cycle is required to
update a new ratio. Internal power-on occurs rapidly.
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