參數(shù)資料
型號(hào)： UL635H256SK55
元件分類： DRAM
英文描述： 256 Kbit serial SPI bus EEPROM with high-speed clock
中文描述： NVRAM中（EEPROM的基礎(chǔ)）
文件頁數(shù)： 1/13頁
文件大?。?/td> 134K
代理商： UL635H256SK55
1
November 01, 2001
UL635H256
Pin Configuration
Pin Description
Signal Name
Signal Description
A0 - A14
DQ0 - DQ7
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
E
G
W
VCC
VSS
G
A11
A9
A8
A13
W
n. c.
VCC
n. c.
A14
A12
A7
A6
A5
A4
A3
n.c.
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
n.c.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
TSOP
Top View
28
27
26
25
24
23
22
21
20
19
18
17
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
SOP
Top View
25
24
23
22
21
20
19
18
17
16
15
Low Voltage
PowerStore
32K x 8 nvSRAM
High-performance CMOS non-
volatile static RAM 32768 x 8 bits
45 and 55 ns Access Times
20 and 25 ns Output Enable
Access Times
I
CC
= 8 mA at 200 ns Cycle Time
Automatic STORE to EEPROM
on Power Down using system
capacitance
Software initiated STORE
Automatic STORE Timing
10
5
STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
Unlimited RECALL cycles from
EEPROM
Wide voltage range: 2.7 ... 3.6 V
Operating temperature range:
0 to 70
-40 to 85
CECC 90000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
Packages: SOP28 (330 mil)
TSOP32 (Type I)
°
C
°
C
The UL635H256 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The UL635H256 is a fast static
RAM (45 and 55 ns), with a nonvo-
latile electrically erasable PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in system
capacitance. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on powerup.
The UL635H256 combines the
high performance and ease of use
of a fast SRAM with nonvolatile
data integrity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Features
Description
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