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參數(shù)資料
| 型號(hào)： | UHC124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Four-Port Embedded USB Host Controller |
| 中文描述： | 高性能四端口嵌入式USB主機(jī)控制器 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 178K |
| 代理商： | UHC124 |
TransDimension
UHC124
Product Brief
TransDimension Inc. — Proprietary
2
Architecture
Development
Interface with MCUs:
The UHC124 may be interfaced with a microprocessor using either one of two methods:
For MCUs with standard external data bus, the UHC124 can be interfaced directly via 8 bits of its data bus and
12 bits of its address bus. When the UHC124 operates under this mode, its internal memory blocks, as well as
its control/status registers, are mapped into the processor’s address space.
For MCUs without an external data bus, the UHC124 may be interfaced using an 8-bit output port and an 8-bit
bi-directional port. Under this mode, a built-in, auto incrementing address register allows accessing to a large
block of the UHC124 memory with a single (address) write cycle, followed by as many read/write cycles as the
number of data bytes to be transferred from/to the UHC124.
Control Memory (CM):
The UHC124 controller memory holds up to 16 Transaction Descriptors (XDs) used to
specify up to 16 USB transactions.
Data Memory (DM):
The 2,048 bytes of data memory (DM) built into the UHC124 serve as data buffers shared
between the MCU and USB system.
Batch Processing:
The user software may organize up to 16 USB transactions into a
transaction batch
, or simply
a
batch
. A batch may contain transactions for full-speed (FS: 12 Mbit/sec) and low-speed (LS: 1.5 Mbit/sec) USB
devices, of four types of endpoints (control, bulk, interrupt and isochronous) and all transaction types (SETUP, IN
and OUT). Compared with other USB host controller designs, batch processing is a very important and unique
feature of the UHC124. Our software/hardware co-design overcomes the serious shortcomings of other embedded
USB host controller designs that require an interrupt upon completion of
every
USB transaction. These defficient
designs:
result in significant loss of USB bus bandwidth as the invocation (interrupt latency time) and execution of the
interrupt service routine (ISR), (or of certain portion of the ISR at the minimum,) cannot overlap with USB bus
Memory/
Register
Acce
ss
&
MCU
Interface
PLL
6MHz
USB Host
Control Logic
Control
Memory
(256 Bytes)
Data
Memory
(2K Bytes)
Root Hub
With
Four
Downstream
Ports
12MHz
/INT
/RESET
D
7
..D
0
/CS
/WR
/RD
ADS
12
8
MODE
48MHz
Registers
(16 Bytes)
PwrSav
Host
SIE
PortChange[0:4]
5
OSC
1
OSC
2
LPF
DP
1
, DM
1
/PO
1
, /OC
1
DP
2
, DM
2
/PO
2
, /OC
2
DP
3
, DM
3
/PO
3
, /OC
3
DP
4
, DM
4
/PO
4
, /OC
4
A
11
..A
0
Figure 1 UHC124 block diagram
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