參數(shù)資料
型號(hào): UDA1380
英文描述: Stereo audio coder-decoder for MD, CD and MP3
中文描述: 立體聲音頻編碼器,可用于MD,CD和MP3解碼器
文件頁(yè)數(shù): 28/68頁(yè)
文件大小: 278K
代理商: UDA1380
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2
2
P
P
S
f
U
10.3
READ cycle
Table 14 shows the I
2
C-bus configuration for a READ cycle. The READ cycle is used to read the data values from the internal registers.
The format of the READ cycle is as follows:
1.
The microcontroller starts with a start condition (S).
2.
The first byte (8 bits) contains the device address ‘00110A10’ and a logic 0 (WRITE) for the bit R/W.
3.
This is followed by an acknowledge (A) by the UDA1380.
4.
After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1380 must start.
5.
The UDA1380 acknowledges this register address.
6.
Then the microcontroller generates a repeated start (Sr).
7.
Then the microcontroller generates the device address ‘00110A10’ again, but this time followed by a logic 1 (READ) of the bit R/W.
8.
The UDA1380 sends the two-bytes register contents with the Most Significant (MS) byte first, and then the Least Significant (LS) byte, each time
acknowledged by the microcontroller.
9.
The microcontroller stops this cycle by generating a negative acknowledge (NA).
10. Finally, the UDA1380 frees the I
2
C-bus and the microcontroller can generate a stop condition (P).
Table 14
Master transmitter reads from the UDA1380 registers in the I
2
C-bus mode
INITIAL BYTE
ACKNOWLEDGE FROM UDA1380
ACKNOWLEDGE FROM MICROCONTROLLER
DEVICE
ADDRESS
R/W
REGISTER
ADDRESS
R/W
MSdata
byte
LS data
byte
S
00110A10
0
A
ADDR
A
Sr
00110A10
1
A
MS1
A
LS1
A
...
A
...
A
MSn
A
LSn
NA
P
auto increment if repeated n groups of 2 bytes are transmitted
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