參數(shù)資料
型號(hào)： UDA1345
廠商： NXP Semiconductors N.V.
元件分類： Codec
英文描述： Economy audio CODEC
中文描述： 經(jīng)濟(jì)音頻CODEC
文件頁數(shù)： 7/28頁
文件大?。?/td> 126K
代理商： UDA1345
2000 Apr 18
7
Philips Semiconductors
Preliminary specification
Economy audio CODEC
UDA1345TS
FUNCTIONAL DESCRIPTION
The UDA1345TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clocks (being the system clock itself
and the digital audio interface signals).
The system clock must be locked in frequency to the audio
digital interface input signals.
The BCK clock can be up to 128f
s
, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: f
BCK
= < 128
×
f
WS
.
Important
: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digitalI/O
data interface.
Note
: the sampling frequency range is from 5 to 100 kHz,
however for the 512f
s
clock mode the sampling range is
from 5 to 55 kHz.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1345TS consists of two
5th-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 64.
Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 dB gain block (the pin to select this mode is given in
Section “L3 microcontroller mode”). This block can be
used in applications in which both 1 V (RMS) and
2 V (RMS) input signals can be input to the UDA1345TS.
In applications in which a 2 V (RMS) input signal is used,
a12 k
resistormustbeusedinserieswiththeinputofthe
ADC.Thisformsavoltagedividertogetherwiththeinternal
ADC resistor and ensures that only 1 V (RMS) maximum
is input to the IC. Using this application for a 2 V (RMS)
input signal, the switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
againstthepresenceof anexternal resistorand thesetting
of the gain switch is given in Table 1; the power supply
voltage is assumed to be 3 V.
Table 1
Application modes using input gain stage
Decimation filter (ADC)
The decimation from 64f
s
to 1f
s
is performed in two stages.
The first stage realizes a 4th-order
characteristic.
This filter decreases the sample rate by 8. The second
stage consists of 2 half-band filters and a recursive filter,
each decimating by a factor of 2.
handbook, halfpage
VSSA(ADC)
VDDA(ADC)
VINL
Vref(A)
VINR
VADCN
VADCP
MC1
MP1
VDDD
VSSD
SYSCLK
MP2
MP3
Vref(D)
VSSO
VOUTL
VDDO
VDDA(DAC)
VSSA(DAC)
VOUTR
MC2
MP5
DATAI
DATAO
WS
BCK
MP4
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
UDA1345TS
MGS876
Fig.2 Pin configuration.
RESISTOR
(12 k
)
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present
Present
Absent
Absent
0 dB
6 dB
0 dB
6 dB
2 V (RMS)
1 V (RMS)
1 V (RMS)
0.5 V (RMS)
sin x
---x
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UDA1345TS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Economy audio CODEC
UDA1345TS/N2 制造商:NXP Semiconductors 功能描述:IC CODEC AUDIO 28-SSOP 制造商:NXP Semiconductors 功能描述:IC, CODEC, AUDIO, 28-SSOP
UDA1345TS/N2,112 功能描述:接口—CODEC AUDIO CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1345TS/N2,118 功能描述:接口—CODEC ECONOMY CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
UDA1345TS/N2118 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述:
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