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參數(shù)資料
| 型號： | UD61256JC07 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 256K x 1 DRAM |
| 中文描述： | 256K × 1的DRAM |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 222K |
| 代理商： | UD61256JC07 |
December 12, 1997
Maintenance only
UD61256
1
Features
p
Dynamic random access memory
262144 x 1 bit manufactured
using a CMOS technology
RAS access times 70 ns, 80 ns
TTL-compatible
Three-state output
256 refresh cycles
4 ms refresh cycle time
FAST PAGE MODE
Operating modes: Read, Write,
Read - Write,
RAS only Refresh,
Hidden Refresh with address
transfer
Power Supply Voltage 5 V
Packages
PDIP16
SOJ20/26 (300 mil)
Operating temperature range
0 to 70 °C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90112
p
p
p
p
p
p
p
p
(300 mil)
p
p
Description
Addressing
The UD61256 is a dynamic Write-
Read-memory with random access.
FPM facilitates faster data operation
with predefined row address. Via 9
address inputs the 18 address bits
are transmitted into the internal
address memories in a time-multi-
plex operation. The falling RAS-
edge takes over the row address.
During RAS Low, the column
address together with the CAS
signal are taken over. The selection
of one or more memory circuits can
be made by activation of the RAS
input.
Read-Write-Control
The choice between Read or Write
cycle is made at the W input. HIGH
at the W input causes a Read cycle,
meanwhile LOW leads to a Write
cycle.
Both CAS-controlled and W-control-
led Write cycles are possible with
activated RAS signal.
Data Output Control
The usual state of the data output is
the High-Z state. Whenever CAS is
inactive (HIGH), Q will float (High-Z).
Thus, CAS functions as data output
control.
After access time, in case of a Read
cycle, the output is activated, and it
contains the logic 0“ or 1“.
Q is then valid until CAS returns into
to inactive state (HIGH).
The memory cycle being a Read,
Read-Write or a Write cycle (W-con-
trolled), Q changes from High-Z
state to the active state (0“ or 1“).
After the access time the contents of
the selected cell is available, except
for the Write cycle.
The output remains active until CAS
becomes inactive, irrespective of
RAS becoming inactive or not. The
memory cycle being a Write cycle
(CAS-controlled), the data output
keeps its High-Z state throughout
the whole cycle. This configuration
makes Q fully controllable by the
user merely through the timing of W.
The output storaging the data, they
remain valid from the end of access
time until the start of another cycle.
Pin Configuration
1
A8
VSS
16
2
D
CAS
15
4
RAS
A6
13
5
A0
A3
12
3
Q
14
6
A2
A4
11
7
A1
A5
10
8
VCC
A7
9
W
1
A8
V
26
2
D
CAS
25
4
RAS
A6
23
10
A0
A3
17
3
Q
24
11
A2
A4
16
12
A1
A5
15
13
VCC
A7
14
W
5
n.c.
n.c.
22
9
n.c.
n.c.
18
Pin Description
Signal Name
Signal Description
A0 - A8
D
Address Inputs
Data Input
Read, Write Control
Row Address Strobe
Power Supply Voltage
Ground
Column Address Strobe
Data Output
no connected
W
RAS
UCC
USS
CAS
Q
n.c.
Top View
Top View
256K x 1 DRAM
SOJ
PDIP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UD61256JC08 | 256K x 1 DRAM |
| UDA | RECTIFIERS ASSEMBLIES |
| UDB | RECTIFIERS ASSEMBLIES |
| UDC | RECTIFIERS ASSEMBLIES |
| UDD | RECTIFIERS ASSEMBLIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UD61256JC08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K x 1 DRAM |
| UD61464DC07 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| UD61464DC08 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 Fast Page Mode DRAM |
| UD61466 | 制造商:ZMD 制造商全稱:Zentrum Mikroelektronik Dresden AG 功能描述:64K x 4 DRAM |
| UD61466DC07 | 制造商:ZMD 制造商全稱:Zentrum Mikroelektronik Dresden AG 功能描述:64K x 4 DRAM |
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