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參數(shù)資料
| 型號(hào)： | UCQ5821LW |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS |
| 中文描述： | BiMOS II 8位串行輸入，鎖存驅(qū)動(dòng) |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 121K |
| 代理商： | UCQ5821LW |
2
3
4
5
6
7
8
SERIAL
DATA OUT
SERIAL
DATA IN
OUTPUT
ENABLE
LOGIC
SUPPLY
STROBE
LOGIC
GROUND
CLOCK
CLK
V
ST
OE
DD
1
SUB
POWER
GROUND
S
L
9
10
11
12
13
14
15
16
OUT
1
OUT
2
OUT
3
Dwg. PP-026A
OUT
8
OUT
7
OUT
6
OUT
5
OUT
4
BiMOS II 8-BIT SERIAL-INPUT,
LATCHED DRIVERS
Always order by complete part number, e.g.,
UCN5821A
.
D
2
5821
Note the DIP package and the SOIC package are
electrically identical and share common terminal
number assignments.
A merged combination of bipolar and MOS technology gives
these devices an interface flexibility beyond the reach of standard
logic buffers and power driver arrays. The UCN5821A and
UCN5821LW each have an eight-bit CMOS shift register and
CMOS control circuitry, eight CMOS data latches, and eight
bipolar current-sinking Darlington output drivers.
BiMOS II devices have much higher data-input rates than the
original BiMOS circuits. With a 5 V logic supply, they will
typically operate at better than 5 MHz. With a 12 V supply,
significantly higher speeds are obtained. The CMOS inputs are
compatible with standard CMOS and NMOS logic levels. TTL
circuits may require the use of appropriate pull-up resistors. By
using the serial data output, the drivers can be cascaded for
interface applications requiring additional drive lines.
The UCN5821A are furnished in a standard 16-pin plastic
DIP; the UCN5821LW are in a 16-lead wide-body SOIC for sur-
face-mount applications. The UCN5821A is also available for
operation from -40
°
C to +85
°
C. To order, change the prefix from
‘UCN’ to ‘UCQ’.
FEATURES
I
To 3.3 MHz Data Input Rate
I
CMOS, NMOS, TTL Compatible
I
Internal Pull-Down Resistors
I
Low-Power CMOS Logic & Latches
I
High-Voltage Current-Sink Outputs
I
Automotive Capable
ABSOLUTE MAXIMUM RATINGS
at 25
°
C Free-Air Temperature
Output Voltage, V
OUT
.....................
50 V
Logic Supply Voltage, V
DD
.............
15 V
Input Voltage Range,
V
IN
..................
-0.3 V to V
DD
+ 0.3 V
Continuous Output Current,
I
OUT
.....................................
500 mA
Package Power Dissipation, P
D
Package Code ‘A’..................
2.1 W
Package Code ‘LW’...............
1.5 W
Operating Temperature Range,
T
A
............................ -20
°
C to +85
°
C
Storage Temperature Range,
T
S
.......................... -55
°
C to +150
°
C
Caution: CMOS devices have input static protection
but are susceptible to damage when exposed to
extremely high static electrical charges.
www.allegromicro.com
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