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參數(shù)資料
| 型號： | UCN5910A |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | HIGH-VOLTAGE BiMOS III 10-BIT SERIAL-INPUT, LATCHED DRIVERS |
| 中文描述： | 高壓BiMOS三10位串行輸入，鎖存驅(qū)動 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 139K |
| 代理商： | UCN5910A |
5910
HIGH-VOLTAGE BiMOS III
10-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
Serial
Data
Input
Shift Register Contents
Serial
Data
Output
Latch Contents
Output Contents
Clock
Input I
1
Strobe
Input
I
2
I
3
...
I
N-1
I
N
I
1
I
2
I
3
...
I
N-1
I
N
Blanking
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
H
L
L
L
... L L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON. The information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TIMING CONDITIONS
(T
A
= +25
°
C, V
DD
= 12 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) ...........................................................................
75 ns
Minimum Data Active Time After Clock Pulse
(Data Hold Time) ...............................................................................
75 ns
Minimum Data Pulse Width .............................................................
150 ns
Minimum Clock Pulse Width ...........................................................
100 ns
Minimum Time Between Clock Activation and Strobe....................
300 ns
Minimum Strobe Pulse Width..........................................................
100 ns
Typical Time Between Strobe Activation and
Output Transition.............................................................................
750 ns
B.
C.
D.
E.
F.
G.
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
Dwg. No. A-12,649A
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