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參數(shù)資料
| 型號： | UCC3919PWTR |
| 英文描述： | Power Control/Management |
| 中文描述： | 電源控制/管理 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 156K |
| 代理商： | UCC3919PWTR |
5
UCC1946
UCC2946
UCC3946
Figure 5. Reset circuit timings.
t1:
V
DD
> 1V, RES is guaranteed low.
t2:
V
DD
> programmed threshold, RES remains low for
T
RP
.
t3:
T
RP
expires, RES pulls high.
t4:
Voltage glitch occurs, but is filtered at the RTH pin,
RES remains high.
t5:
Voltage glitch occurs whose magnitude and dura-
tion is greater than the RTH filter, RES is asserted for
T
RP
.
t6:
V
DD
dips below threshold (minus hysteresis), RES
is asserted.
UDG-97067
In order to provide design flexibility, the reset and watch-
dog circuits in the UCC3946 have separate outputs.
Each output will independently drive high or low, depend-
ing on circuit conditions explained previously.
In some applications, it may be desirable for either the
RES or WDO to reset the microprocessor. This can be
done by connecting WDO to RES. If the pins try to drive
to different output levels, the low output level will domi-
nate. Additional current will flow from VDD to GND during
these states. If the application cannot support additional
current (during fault conditions), RES and WDO can be
connected to the inputs of an OR gate whose output is
connected to the microprocessor’s reset pin.
Layout Considerations
A 0.1
μ
F capacitor connected from V
DD
to GND is recom-
mended to decouple the UCC3946 from switching tran-
sients on the V
DD
supply rail.
Since RP and WP are precision current sources, capaci-
tors C
RP
and C
WP
should be connected to these pins
with minimal trace length to reduce board capacitance.
Care should be taken to route any traces with high volt-
age potential or high speed digital signals away from
these capacitors.
Resistors R1 and R2 generally have a high ohmic value,
traces associated with these parts should be kept short
in order to prevent any transient producing signals from
coupling into the high impedance RTH pin.
APPLICATION INFORMATION (cont.)
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