參數(shù)資料
型號: UCC3813PWTR-4
廠商: Texas Instruments, Inc.
英文描述: Low Power Economy BiCMOS Current Mode PWM
中文描述: 低功耗經(jīng)濟(jì)的BiCMOS電流模式PWM
文件頁數(shù): 5/8頁
文件大?。?/td> 215K
代理商: UCC3813PWTR-4
5
UCC2813-0/-1/-2/-3/-4/-5
UCC3813-0/-1/-2/-3/-4/-5
The frequency of oscillation can be estimated with the
following equations:
UCCx813-0/-1/-2/-4: F
R
C
=
15
UCCx813-3, UCCx813-5: F
R
C
=
10
where frequency is in Hz, resistance is in
, and capaci-
tance is in farads. The recommended range of timing re-
sistors is between 10k and 200k and timing capacitor is
100pF to 1000pF. Never use a timing resistor less than
10k.
GND:
GND is reference ground and power ground for all
functions on this part.
OUT:
OUT is the output of a high-current power driver
capable of driving the gate of a power MOSFET with
peak currents exceeding
±
750mA. OUT is actively held
low when VCC is below the UVLO threshold.
The high-current power driver consists of FET output de-
vices, which can switch all of the way to GND and all of
the way to VCC. The output stage also provides a very
low impedance to overshoot and undershoot. This means
that in many cases, external schottky clamp diodes are
not required.
VCC:
VCC is the power input connection for this device.
In normal operation VCC is powered through a current
limiting resistor. Although quiescent VCC current is very
low, total supply current will be higher, depending on
OUT current. Total VCC current is the sum of quiescent
VCC current and the average OUT current. Knowing the
operating frequency and the MOSFET gate charge (Qg),
average OUT current can be calculated from:
I
Q
F
OUT
g
=
.
To prevent noise problems, bypass VCC to GND with a
ceramic capacitor as close to the VCC pin as possible.
An electrolytic capacitor may also be used in addition to
the ceramic capacitor.
REF:
REF is the voltage reference for the error amplifier
and also for many other functions on the IC. REF is also
used as the logic power supply for high speed switching
logic on the IC.
When VCC is greater than 1V and less than the UVLO
threshold, REF is pulled to ground through a 5k
resis-
tor. This means that REF can be used as a logic output
indicating power system status. It is important for refer-
ence stability that REF is bypassed to GND with a ce-
ramic capacitor as close to the pin as possible. An
electrolytic capacitor may also be used in addition to the
ceramic capacitor. A minimum of 0.1
μ
F ceramic is re-
quired. Additional REF bypassing is required for external
loads greater than 2.5mA on the reference.
To prevent noise problems with high speed switching
transients, bypass REF to ground with a ceramic capaci-
tor very close to the IC package.
PIN DESCRIPTIONS (cont.)
Figure 1. Oscillator.
APPLICATION INFORMATION
The UCC3813-0/-1/-2/-3/-4/-5 oscillator generates a sawtooth waveform on RC. The rise time is set by the time constant of R
T
and C
T
. The fall time is set by CT and an internal transistor on-resistance of approximately 125
. During the fall time, the output
is off and the maximum duty cycle is reduced below 50% or 100% depending on the part number. Larger timing capacitors in-
crease the discharge time and reduce the maximum duty cycle and frequency.
UDG-96139
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