參數(shù)資料
型號: UCC2974
廠商: Texas Instruments, Inc.
英文描述: DUAL COLD CATHODE FLUORESCENT LAMP CONTROLLER
中文描述: 雙冷陰極熒光燈控制器
文件頁數(shù): 7/12頁
文件大?。?/td> 210K
代理商: UCC2974
SLUS485A
JULY 2001
REVISED NOVEMBER 2001
7
www.ti.com
1 OUT1
16
OUT2
2 VIN
15
GND
3 OUT1
14
OUT2
4 COMP1
13
CBP
5 FB1
12
COMP2
6 RT1
11
FB2
7 RT2
10
MODE
8 DIM
9
LFDSYNC
C8 1
μ
F
C7
C6
1
μ
F
R9
10
UCC3974
100
μ
F
35 V
R10
10
VIN
C5
10 nF
100
μ
F
35 V
D2
Q2
Q1
VIN
R2
750
VIN
C3
C2
33 pF
3 kV
D1
BRIGHT
SYNC
100
μ
F
35 V
L2
100
μ
H
D3
Q3
Q4
VIN
R6
750
VIN
C8
C9
33 pF
3 kV
R7
750
D4
T2
T1
Q5
Q6
R3
C4
R8 200 k
R4 20 k
R5
R12
10 k
R11
10 k
UDG
01020
R1
750
Figure 1. Typical Dual-Channel Application
low-frequency dimming (LFD)
The low-frequency dimming section of the device is implemented as either a low frequency pulse width
modulator (PWM) or as a direct digital input. In either case, the DIM pin is the controlling input. The type of DIM
input is determined at startup. As the MODE pin transitions through the LFD_ENABLE threshold, the LFDSYNC
pin is observed. When this pin is high, the DIM pin is a 2.5-V compatible logic input. When the DIM pin is high,
the output is enabled. When it is low the output is disabled. The user is required to provide the correct frequency
and duty ratio to the DIM pin in this mode. To change the mode of operation without power cycling the device,
the MODE pin must be brought below the LFD_ENABLE threshold and then brought above it with the LFDSYNC
pin held in the desired state.
To use DIM as an analog input, the LFDSYNC pin must be low when mode crosses the LFD_ENABLE threshold.
In this mode, DIM becomes an analog input that varies the amount of time that the lamp is on during the period
of the LFD oscillator. From 0.5 V to 3 V applied to the DIM pin varies the lamp on duty cycle from the programmed
minimum to 100%.
NOTE:
The analog dimming signal is senitive to coupled noise from the lamps. Noise on this line
will be seen as lamp flicker. It is highly reccommended that precautions be taken to prevent noise
coupling to this signal for optimum results.
Applying a pulse train to the LFDSYNC pin will synchronize the LFD oscillator to that pulse train. The frequency
of the applied pulse train must be higher than the free running frequency of the oscillator.
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