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參數(shù)資料
| 型號(hào)： | UCC2961N |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
| 中文描述： | 5.0放大器正電壓穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 156K |
| 代理商： | UCC2961N |
4
UCC1946
UCC2946
UCC3946
The UCC3946 allows the reset trip voltage to be pro-
grammed with two external resistors. In most applica-
tions VDD is monitored by the reset circuit, however, the
design allows voltages other than VDD to be monitored.
Referring to Fig. 4, the voltage below which reset will be
asserted is determined by:
=1.235 R1+R2
R2
In order to keep quiescent currents low, resistor values in
the megaohm range can be used for R1 and R2. A man-
ual reset can be easily implemented by connecting a mo-
mentary push switch in parallel with R2. RES is
guaranteed to be low with VDD voltages as low as 1V.
V
RESET
Once VDD rises above the programmed threshold, RES
remains low for the reset period defined by:
T
C
RP
RP
=
3 125
.
where T
RP
is time in milliseconds and C
RP
is capacitance
in nanofarads. C
RP
is charged with a precision current
source of 400nA, a high quality, low leakage capacitor
(such as an NPO ceramic) should be used to maintain
timing tolerances. Fig. 5 illustrates the voltage levels and
timings associated with the reset circuit.
Programming the Watchdog Period
The watchdog period is programmed with C
WP
as fol-
lows:
T
C
WP
WP
=
25
where T
WP
is in milliseconds and C
WP
is in nanofarads.
A high quality, low leakage capacitor should be used for
C
WP.
The watchdog input WDI must be toggled with a
high/low or low/high transition within the watchdog period
to prevent WDO from assuming a logic level low. WDO
will maintain the low logic level until WDI is toggled or
RES is asserted. If at any time RES is asserted, WDO
will assume a high logic state and the watchdog period
will be reinitiated. Fig. 6 illustrates the timings associated
with the watchdog circuit.
Connecting WDO to RES
6
7
WDI
WP
8
VDD
3
5
POWER TO
CIRCUITRY
A3
A2
A1
A0
CLK
CLR
8-BIT COUNTER
400nA
WDO
1
GND
EDGE DETECT
WATCHDOG TIMING
100mV
1.235V
2
RTH
4
RP
400nA
POWER ON RESET
R1
VDD
R2
RESET
NMI
I/O
uP
RES
C
WP
1.235V
C
RP
Figure 4. Typical application diagram.
APPLICATION INFORMATION (cont.)
UDG-98002
Note: Pinout represents the 8-pin TSSOP package.
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