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參數(shù)資料
| 型號： | UCC284SDR-5EP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 固定負電壓單路輸出LDO穩(wěn)壓器 |
| 英文描述： | 5 V FIXED NEGATIVE LDO REGULATOR, 0.55 V DROPOUT, PDSO8 |
| 封裝： | GREEN, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 506K |
| 代理商： | UCC284SDR-5EP |
R3 +
0.9
t
M
seconds
C2(F)
n
1 *
V
IN
(V)*1.6
V
IN
(V)
Ohms
(9)
minimum VIN to VOUT delay time
thermal design
t
RISE +
P
DISS
(qjc ) qca)
(10)
Pavg + VIN(V) * VOUT(V)
I
PEAK
(A)
t
ON
(seconds)
40
t
ON
(seconds)
Watts
(11)
www.ti.com ....................................................................................................................................... SLVS862A – NOVEMBER 2008 – REVISED NOVEMBER 2008
R3 along with C2 set the time that Q1 is allowed to be on. Since tM is the maximum amount of time that Q1
should be allowed to stay on, an added safety margin may be to use 0.9 × tM instead. This ensures that Q1 is
turned off in the proper amount of time. With a chosen value for C2, R3 can be calculated as follows:
After the CT capacitor has charged up for a time equal to 0.9 × tM, Q1 turns off and allows the SD/CT pin to be
pulled back to –1.5 V with respect to GND through a 50-k
resistor. At this point, the SD/CT pin can be used by
the UCC284 overcurrent timing control.
Although it may desirable to have as short a delay time as possible, a small portion of this delay time is fixed by
the UCC284 and cannot be shortened. This is shown in Figure 12, where the CT capacitor has been removed
from the circuit completely, giving a fixed VIN to VOUT delay of approximately 150
s for a circuit with
VIN = –6 V and VOUT = –5 V.
The Packaging Information section of the Power Supply Control Products Data Book (literature number
SLUD003) contains reference material for the thermal ratings of various packages. The section also includes an
excellent article entitled Thermal Characteristics of Surface Mount Packages, which is the basis for the following
discussion.
Thermal design for the UCC284 includes two modes of operation, normal and pulsed. In normal mode, the linear
regulator and heat sink must dissipate power equal to the maximum forward voltage drop multiplied by the
maximum load current. Assuming a constant current load, the expected heat rise at the regulator’s junction can
be calculated as follows:
Theta (
θ) is the thermal resistance and PDISS is the power dissipated. The junction-to-case thermal resistance
(
θjc) of the SOIC-8 D package is 22°C/W. In order to prevent the regulator from going into thermal shutdown, the
case-to-ambient thermal resistance (
θca) must keep the junction temperature below 150°C. If the UCC284 is
mounted on a 5 square inch pad of 1-ounce copper, for example, the thermal resistance (
θja) becomes
40-70°C/W. If a lower thermal resistance is required for the application, the device heat sinking needs to be
improved.
When the UCC284 is in a pulsed mode, due to an overcurrent condition, the maximum average power
dissipation is calculated as follows:
As seen in equation (10), the average power during a fault is reduced dramatically by the duty cycle, allowing the
heat sink to be sized for normal operation. Although the peak power in the regulator during the tON period can be
significant, the thermal mass of the package normally keeps the junction temperature from rising unless the tON
period is increased to several milliseconds.
Copyright 2008, Texas Instruments Incorporated
15
Product Folder Link(s): UCC284-EP
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