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參數(shù)資料
| 型號： | UCC2809 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Economy Primary Side Controller |
| 中文描述： | 經(jīng)濟初級側控制器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 131K |
| 代理商： | UCC2809 |
5
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
The Typical Application Diagram shows an isolated
flyback converter utilizing the UCC3809. Note that the
capacitors C
REF
and C
VDD
are local decoupling capaci-
tors for the reference and IC input voltage, respectively.
Both capacitors should be low ESR and ESL ceramic,
placed as close to the IC pins as possible, and returned
directly to the ground pin of the chip for best stability.
REF provides the internal bias to many of the IC func-
tions and C
REF
should be at least 0.47
μ
F to prevent REF
from drooping.
FB Pin
The basic premise of the UCC3809 is that the voltage
sense feedback signal originates from an optocoupler
that is modulated by an external error amplifier located
on the secondary side. This signal is summed with the
current sense signal and any slope compensation at the
FB pin and compared to a 1V threshold, as shown in the
Typical Application Diagram. Crossing this 1V threshold
resets the PWM latch and modulates the output driver
on-time much like the current sense comparator used in
the UC3842. In the absence of a FB signal, the output
will follow the programmed maximum on-time of the os-
cillator.
When adding slope compensation, it is important to use
a small capacitor to AC couple the oscillator waveform
before summing this signal into the FB pin. By correctly
selecting the emitter resistor of the optocoupler, the volt-
age sense signal can force the FB node to exceed the
1V threshold when the output that is being compared ex-
ceeds a desired level. Doing so drives the UCC3809 to
zero percent duty cycle.
Oscillator
The following equation sets the oscillator frequency:
(
[
(
D
RT
CT
MAX
074
1
.
Referring to Figure 2 and the waveforms in Figure 3,
when Q1is on, CT charges via the R
DS(on)
of Q1 and
RT1. During this charging process, the voltage of CT is
sensed through RT2. The S input of the oscillator latch,
S(OSC), is level sensitive, so crossing the upper thresh-
old (set at 2/3 VREF or 3.33V for a typical 5.0V refer-
ence) sets the Q output (CLK signal) of the oscillator
latch high. A high CLK signal results in turning off Q1
and turning on Q2. CT now discharges through RT2 and
the R
DS(on)
of Q2.
CT discharges from 3.33V to the
lower threshold (set at 1/3 VREF or 1.67V for a typical
) (
)
]
F
CT
pF
RT
RT
OSC
=
+
+
074
.
27
1
2
1
)
pF
F
OSC
=
+
27
5.0V reference) sensed through RT1. The R input to the
oscillator latch, R(OSC), is also level sensitive and resets
the CLK signal low when CT crosses the 1.67V thresh-
old, turning off Q2 and turning on Q1, initiating another
charging cycle.
Figure 3 shows the waveforms associated with the oscil-
lator latch and the PWM latch (shown in the Typical Ap-
plication Diagram). A high CLK signal not only initiates a
discharge cycle for CT, it also turns on the internal
NMOS FET on the FB pin causing any external capaci-
tance used for leading edge blanking connected to this
pin to be discharged to ground. By discharging any ex-
ternal capacitor completely to ground during the external
switch’s off-time, the noise immunity of the converter is
enhanced allowing the user to design in smaller RC com-
ponents for leading edge blanking.
also sets the level sensitive S input of the PWM latch,
S(PWM), high, resulting in a high output, Q(PWM), as
shown in Figure 3. This Q(PWM) signal will remain high
until a reset signal, R(PWM) is received. A high R(PWM)
signal results from the FB signal crossing the 1V thresh-
old, or during soft start or if the SS pin is disabled.
A high CLK signal
Assuming the UVLO threshold is satisfied, the OUT sig-
nal of the IC will be high as long as Q(PWM) is high and
S(PWM), also referred to as CLK, is low. The OUT sig-
nal will be dominated by the FB signal as long as the FB
signal trips the 1V threshold while CLK is low. If the FB
signal does not cross the 1V threshold while CLK is low,
the OUT signal will be dominated by the maximum duty
cycle programmed by the user. Figure 3 illustrates the
various waveforms for a design set up for a maximum
duty cycle of 70%.
APPLICATION INFORMATION (cont.)
S
Q
R
Q2
Q1
3
4
RT2
CT
RT1
V
REF
3.33V
1.67V
CLK
OSC
OSCILLATOR
LATCH
Figure 2. UCC3809 oscillator.
UDG-97195
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UCC2809-1 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Economy Primary Side Controller |
| UCC2809-2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Economy Primary Side Controller |
| UCC2809D-1 | 功能描述:初級與次級側 PWM 控制器 Economy Primary Side Controller RoHS:否 制造商:ON Semiconductor 輸出端數(shù)量:1 開關頻率:250 KHz 工作電源電壓:- 0.3 V to + 28 V 最大工作溫度:+ 85 C 最小工作溫度:- 5 C 封裝 / 箱體:SOIC-8 Narrow 封裝:Reel |
| UCC2809D-1G4 | 功能描述:初級與次級側 PWM 控制器 Economy Primary Side Controller RoHS:否 制造商:ON Semiconductor 輸出端數(shù)量:1 開關頻率:250 KHz 工作電源電壓:- 0.3 V to + 28 V 最大工作溫度:+ 85 C 最小工作溫度:- 5 C 封裝 / 箱體:SOIC-8 Narrow 封裝:Reel |
| UCC2809D-2 | 功能描述:初級與次級側 PWM 控制器 Economy Primary Side Controller RoHS:否 制造商:ON Semiconductor 輸出端數(shù)量:1 開關頻率:250 KHz 工作電源電壓:- 0.3 V to + 28 V 最大工作溫度:+ 85 C 最小工作溫度:- 5 C 封裝 / 箱體:SOIC-8 Narrow 封裝:Reel |
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