參數(shù)資料
型號: UCC2752D
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Very low drop voltage regulators with inhibit
中文描述: 電話鈴聲
文件頁數(shù): 2/7頁
文件大?。?/td> 103K
代理商: UCC2752D
2
UCC2751
UCC3751
DIL-16, SOIC-16 (TOP VIEW)
N or D Packages
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Analog Inputs (OHD, DCLIM, XTAL1, XTAL2)
Maximum Forced Voltage. . . . . . . . . . . . . . . . . . . . –0.3 to 5V
Logic Inputs
Maximum Forced Voltage . . . . . . . . . . . . . . . . . . –0.3 to 7.5V
Reference Output Current (V
DD)
. . . . . . . . . . . Internally Limited
Output Current (DRV1, DRV2, DRVS) Pulsed . . . . . . . . . . 1.5A
Operating Junction Temperature . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Note: Unless otherwise indicated, voltages are referenced to
ground and currents are positive into, negative out of, the spe-
cific terminals. Pulsed is defined as a less than 10% duty cycle
with a maximum duration of 500 S.
PGND
XTAL2
XTAL1
DRV2
DRVS
ENABLE
DRV1
VS12
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
RINGEN
DELAY
FS1
OHD
FS0
GND
V
DD
DCLIM
CONNECTION DIAGRAM
11
4
13
OHD
DRV1
RINGEN
14
9
3
12
DELAY
FS0
FS1
2
6
1
DRVS
VDD
GND
VS12
7
8
DRV2
PGND
5 VOLT
REFERENCE
ONE-SHOT
1/F
OSC
4.5V
CLR
CLK
PROGRAMMABLE
COUNTER
MODULO
40
COUNTER
MODULO
3,560
COUNTER
MODULO
1,800
COUNTER
MODULO
4,480
COUNTER
2/F
OSC
ONE-SHOT
2 BIT
A/D
300mV
DCLIM
5
300mV
XTAL1
16
XTAL2
15
10
MODULO
2
COUNTER
ENABLE
MODULO
20
COUNTER
ONE-SHOT
BLOCK DIAGRAM
UDG-98020
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