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參數(shù)資料
| 型號(hào)： | UCC2626PW |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 直流電機(jī)控制器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 7/19頁(yè) |
| 文件大?。?/td> | 336K |
| 代理商： | UCC2626PW |
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SLUS318B
–
APRIL 1999
–
REVISED JANUARY 2002
7
www.ti.com
pin descriptions
SYNCH
: The SYNCH input is used to synchronize the PWM oscillator with an external digital clock. When using
the SYNCH feature, a resistor equal to R_TACH must be placed in parallel with CT. When not using the SYNCH
feature, SYNCH must be grounded.
SNS_NI, SNS_I
: These inputs are the noninverting and inverting inputs to the current sense amplifier,
respectively. The integrated amplifier is configured for a gain of five. An absolute value function is also
incorporated into the output in order to provide a representation of actual motor current when operating in
four-quadrant mode.
TACH_OUT
: TACH_OUT is the output of a monostable triggered by a change in the commutation state, thus
providing a variable duty cycle, frequency output. The on time of the monostable is set by the timing capacitor
connected to C_TACH. The monostable is capable of being retriggered if a commutation occurs during its
on-time.
R_TACH
: A resistor connected between R_TACH and ground programs the current for both the oscillator and
tachometer.
VDD
: VDD is the input supply connection for this device. Undervoltage lockout keeps the outputs off for inputs
below 10.5 V. The input should be bypassed with a 0.1-
μ
F ceramic capacitor, minimum.
VREF
: VREF is a 5-V, 2% trimmed reference output with 5 mA of maximum available output current. This pin
should be bypassed to ground with a ceramic capacitor with a value of at least 0.1
μ
F.
APPLICATION INFORMATION
Table 1 provides the decode logic for the six outputs, AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function
of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and HALLC inputs.
Table 1. Commutation Truth Table
BRAKE
COAST
DIR_IN
HALL
INPUTS
B
0
0
1
1
1
0
0
0
1
1
1
0
X
X
1
0
HIGH-SIDE
OUTPUTS
A
B
1
0
1
0
0
1
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
LOW-SIDE
OUTPUTS
A
B
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
0
0
0
0
A
1
1
1
0
0
0
1
0
0
0
1
1
X
X
1
0
C
1
0
0
0
1
1
1
1
1
0
0
0
X
X
1
0
C
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
C
0
1
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
X
X
X
X
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