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參數(shù)資料
| 型號(hào)： | UCC1581J |
| 英文描述： | Very low drop and low noise voltage regulator low ESR capacitors compatible, with inhibit function |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | UCC1581J |
3
UCC1581
UCC2581
UCC3581
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for VDD = 10V, 0.1
μ
F capacitor
from VDD to GND, 1.0
μ
F capacitor from REF to GND, RT1 = 680k
, RT2 = 12k
, CT = 750pF and T
A
= T
J
.
PARAMETER
Current Sense Section
Input Bias Current
Overcurrent Threshold
Output Section
OUT Low Level
I = 100mA
OUT High Level
I = –100mA, VDD – OUT
Rise/Fall Time
(Note 1)
Soft start Section
Soft start Current
SS = 2V
Chip Enable Section
VIH
VIL
Hysteresis
Source Current
Overall Section
Start-Up Current
VDD < Start Threshold
Operating Supply Current
VC = 0V
VDD Zener Shunt Voltage
I
DD
= 10mA
I
DD
Stand-by Shunt Voltage
EN = 0V
TEST CONDITIONS
MIN
TYP
MAX
UNITS
–150
0.4
20
0.5
150
0.6
nA
V
0.6
0.6
20
1.2
1.2
100
V
V
ns
–9
–11.5
–14
μ
A
1.9
1.7
180
5
2.0
1.8
230
10
2.1
1.9
280
15
V
V
mV
μ
A
85
300
15
100
130
600
16.5
150
μ
A
μ
A
V
μ
A
13.5
Note 1: Guaranteed by design. Not 100% tested in production
CT:
Oscillator timing capacitor pin. Minimum value is
100pF.
DCMIN:
Input for programming minimum duty cycle
where pulse skipping begins. This pin can be grounded
to disable minimum duty cycle feature and pulse
skipping.
EN:
Enable input. This pin has an internal 10
μ
A pull-up. A
logic low input inhibits the PWM output and causes the
soft start capacitor to be discharged.
GND:
Circuit ground.
GT:
Pin for controlling the gate of an external depletion
mode N-MOSFET for the startup supply. The external
N-MOSFET regulates VDD to 7.5V until the bootstrap
supply comes up, then GT goes low.
ISEN:
Input for overcurrent comparator. This function can
be used for pulse-by-pulse current limiting. The threshold
is 0.5V nominal.
OUT:
Gate drive output to external N-MOSFET.
REF:
4.0V reference output. A minimum value bypass
capacitor of 1.0
μ
F is required for stability.
RT1:
Resistor pin to program oscillator charging current.
The oscillator charging current is 9 2
2 0
.
RT
1
.
V
.
See Application Diagram Fig. 1.
The current into this pin is
2. V
RT
1
.
The value of RT1 should be between 220k and 1M
.
RT2:
Resistor pin to program oscillator discharge time.
The minimum value of RT2 is 10k
. See Application
Diagram Fig. 1.
SS:
Soft start capacitor pin. The charging current out of
SS is 3.75X the current in RT1.
SYNC:
Oscillator
triggered CMOS/TTL compatible input with a 2.1V
threshold. SYNC should be grounded if not used. The
minimum pulse width of the SYNC signal is 100ns.
synchronization
pin. Rising
edge
VC:
Control voltage input to PWM comparator. The
nominal control range of VC is 1.0V to 2.5V.
VDD:
Chip input power with an 15V internal clamp. VDD
is regulated by startup FET to 7.5V until the bootstrap
voltage comes up. VDD should be bypassed at the chip
with a 0.1
μ
F minimum capacitor.
PIN DESCRIPTIONS
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|---|---|
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