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參數(shù)資料
| 型號： | UCC1580DTR-4 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Ultra low drop voltage regulators with inhibit low ESR output capacitors compatible |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 371K |
| 代理商： | UCC1580DTR-4 |
6
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
The soft start pin provides an effective means to start
the IC in a controlled manner. An internal current of
20
μ
A begins charging a capacitor connected to SS once
the startup conditions listed above have been met. The
voltage on SS effectively controls maximum duty cycle
on OUT1 during the charging period. OUT2 is also con-
trolled during this period (see Figure 1). Negation of any
of the startup conditions causes SS to be immediately
discharged. Internal circuitry ensures full discharge of
SS (to 0.3V) before allowing charging to begin again,
provided all the startup conditions are again met.
Oscillator
Simplified oscillator block diagram and waveforms are
shown in Figure 3. OSC1 and OSC2 pins are used to
program the frequency and maximum duty cycle. Ca-
pacitor CT is alternately charged through R1 and dis-
charged through R2 between levels of 1V and 3.5V. The
charging and discharging equations for CT are given by
VC(charge)=REF – 4.0 e
-
t
1
τ
VC(discharge)= 3.5 e
-
t
2
τ
where
τ
1
= R1 CT and
τ
2
= R2 CT. The charge time
and discharge time are given by
t
CH
= R1 C
T
and t
DIS
= 1.25 R2 C
T
The CLK output is high during the discharge period. It
blanks the output to limit the maximum duty cycle of
OUT1. The frequency and maximum duty cycle are
given by
1
(R1+1.25 R2)CT
Frequency =
MaximumDutyCycle =
R1
R1+1.25 R2
Maximum Duty Cycle for OUT1 will be slightly less due
to Delay1 which is programmed by R3.
Voltage Feedforward and Volt-Second Clamp
UCC3580 has a provision for input voltage feedforward.
As shown in Figure 3, the ramp slope is made propor-
tional to input line voltage by converting it into a charg-
ing
current
for
CR.
This
cancellation of the effects of line voltage changes on
converter
performance.
The
clamp is provided to protect against transient saturation
of the transformer core. It terminates the OUT1 pulse
when
the
RAMP
voltage
feedforward feature is not used, the ramp can be gener-
ated by tying R4 to REF. However, the linearity of ramp
suffers and in this case the maximum volt-second clamp
is no longer available.
provides
a
first
order
maximum
volt-second
exceeds
3.3V.
If
the
Figure 3. Oscillator and ramp circuits.
UDG-96016-1
DelayTimes
0
200
400
600
800
1000
1200
1400
0
100
200
300
400
500
600
700
800
900
1000
R3 ProgrammingResistor [k
]
D
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
D
Delay Ratio
Delay1
Delay2
Figure 2. Delay times.
APPLICATION INFORMATION (cont.)
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UCC1580J-1 | Ultra low drop voltage regulators with inhibit low ESR output capacitors compatible |
| UCC1580QTR-1 | Very low drop and low noise voltage regulator with inhibit function, low ESR capacitors compatible |
| UCC1580QTR-2 | Very low drop and low noise voltage regulator low ESR capacitors compatible, with inhibit function |
| UCC1580QTR-3 | Very low drop and low noise voltage regulator low ESR capacitors compatible, with inhibit function |
| UCC1580QTR-4 | Very low drop and low noise voltage regulator low ESR capacitors compatible, with inhibit function |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UCC1580J-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Mode SMPS Controller |
| UCC1580J-2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Single Ended Active Clamp/Reset PWM |
| UCC1580J-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| UCC1580J-4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Single Ended Active Clamp/Reset PWM |
| UCC1580N-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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