- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380964 > UCC1580DTR-3 Ultra low drop voltage regulators with inhibit low ESR output capacitors compatible PDF資料下載
參數(shù)資料
| 型號(hào)： | UCC1580DTR-3 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Ultra low drop voltage regulators with inhibit low ESR output capacitors compatible |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 371K |
| 代理商： | UCC1580DTR-3 |
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
Powered by ICminer.com Electronic-Library Service CopyRight 2003
FEATURES
Provides Auxiliary Switch Activation
Complementary to Main Power
Switch Drive
Programmable deadtime (Turn-on
Delay) Between Activation of Each
Switch
Voltage Mode Control with
Feedforward Operation
Programmable Limits for Both
Transformer Volt- Second Product
and PWM Duty Cycle
High Current Gate Driver for Both
Main and Auxiliary Outputs
Multiple Protection Features with
Latched Shutdown and Soft Restart
Low Supply Current (100
μ
A Startup,
1.5mA Operation)
BLOCK DIAGRAM
DESCRIPTION
The UCC3580 family of PWM controllers is designed to implement a variety
of active clamp/reset and synchronous rectifier switching converter topolo-
gies. While containing all the necessary functions for fixed frequency, high
performance pulse width modulation, the additional feature of this design is
the inclusion of an auxiliary switch driver which complements the main
power switch, and with a programmable deadtime or delay between each
transition. The active clamp/reset technique allows operation of single
ended converters beyond 50% duty cycle while reducing voltage stresses
on the switches, and allows a greater flux swing for the power transformer.
This approach also allows a reduction in switching losses by recovering en-
ergy stored in parasitic elements such as leakage inductance and switch
capacitance.
The oscillator is programmed with two resistors and a capacitor to set
switching frequency and maximum duty cycle.
ramp provides a voltage feedforward pulse width modulation and a pro-
grammed maximum volt-second limit. The generated clock from the oscilla-
tor contains both frequency and maximum duty cycle information.
A separate synchronized
(continued)
Single Ended Active Clamp/Reset PWM
UDG-95069-2
Pin Numbers refer to DIL-16 and SOIC-16 packages
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UCC1580DTR-4 | Ultra low drop voltage regulators with inhibit low ESR output capacitors compatible |
| UCC1580J-1 | Ultra low drop voltage regulators with inhibit low ESR output capacitors compatible |
| UCC1580QTR-1 | Very low drop and low noise voltage regulator with inhibit function, low ESR capacitors compatible |
| UCC1580QTR-2 | Very low drop and low noise voltage regulator low ESR capacitors compatible, with inhibit function |
| UCC1580QTR-3 | Very low drop and low noise voltage regulator low ESR capacitors compatible, with inhibit function |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UCC1580DTR-4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| UCC1580J-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Mode SMPS Controller |
| UCC1580J-2 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Single Ended Active Clamp/Reset PWM |
| UCC1580J-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| UCC1580J-4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Single Ended Active Clamp/Reset PWM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。