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參數(shù)資料
| 型號(hào)： | UC62LV4096AC-25 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Low Power CMOS SRAM |
| 中文描述： | 低功耗CMOS SRAM |
| 文件頁(yè)數(shù)： | 7/9頁(yè) |
| 文件大?。?/td> | 145K |
| 代理商： | UC62LV4096AC-25 |
Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
WRITE CYCLE2
(1,6)
t
WC
ADDRESS
t
DH
t
WHZ
WE
D
OUT
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
D
IN
t
DW
t
OH
(8)
(7)
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. T
WR
is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE\ going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
PAGE
7
Preliminary
Rev. 1.0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UC62LV4096AI-20 | Low Power CMOS SRAM |
| UC62LV4096AI-25 | Low Power CMOS SRAM |
| UC62LV4096JC-20 | Low Power CMOS SRAM |
| UC62LV4096JC-25 | Low Power CMOS SRAM |
| UC62LV4096JI-20 | Low Power CMOS SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UC62LV4096AI-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096AI-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096JC-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096JC-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
| UC62LV4096JI-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Low Power CMOS SRAM |
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