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參數(shù)資料
| 型號(hào)： | UC621XX-AF5-R |
| 廠商： | 友順科技股份有限公司 |
| 英文描述： | CMOS IC |
| 中文描述： | CMOS集成電路 |
| 文件頁(yè)數(shù)： | 5/14頁(yè) |
| 文件大小： | 199K |
| 代理商： | UC621XX-AF5-R |
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UC621XX
CMOS IC
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
5 of 14
QW-R502-028,B
ELECT RICAL CHARACT ERIS T ICS (Cont.)
UC62140
(V
OUT(T)
=4.0V)
PARAMETER
Output Voltage (Note2)
Input Voltage
EXT Output Voltage
SYMBOL
V
OUT(E)
V
IN
V
EXT
V
CEH
V
CEL
V
OUT
V
DIFF
I
OUT (max)
Iss1
Iss2
I
LEAK
I
CEH
I
CEL
V
OUT
V
IN
V
OUT
T
OPR
TEST CONDITIONS
I
OUT
=50mA, V
IN
=5.0V
MIN
3.92
1.5
-60
-0.2
TYP
4.000
100
1000
50
-0.05
MAX
4.08
8
8
0.25
60
UNIT
V
V
V
V
V
mV
mV
mA
μA
μA
μA
μA
μA
High
Low
CE Level Voltage
Load Stability (Note 4)
Input-Output Voltage Differential
Maximum Output Current(Note 4)
Supply Current1
Supply Current2
EXT Leakage Current
V
IN
=5.0V, 1mA
I
OUT
=100mA
V
IN
=5.0V
V
IN
=5.0V, V
CE
=Vss
V
IN
=8.0V, V
CE
=V
IN
I
OUT
100mA
0.6
80
0.5
0.1
0
High
Low
V
CE
=V
IN
V
CE
=Vss
CE Level Current
Input Stability (Note 4)
V
OUT
I
OUT
=50mA, 5.0V
≤
V
IN
≤
8.0V
0.1
0.3
%/V
Output Voltage Temperature
Characteristics (Note 4)
V
OUT
I
OUT
=10mA, -20
≤
T
OPR
≤
85
100
ppm/
UC62150
(V
OUT(T)
=5.0V)
PARAMETER
SYMBOL
Output Voltage (Note2)
V
OUT(E)
I
OUT
=50mA, V
IN
=6.0V
Input Voltage
V
IN
EXT Output Voltage
V
EXT
High
V
CEH
CE Level Voltage
Low
V
CEL
Load Stability (Note 4)
V
OUT
V
IN
=6.0V, 1mA
≤
I
OUT
≤
100mA
Input-Output Voltage Differential
V
DIFF
I
OUT
=100mA
Maximum Output Current(Note 4)
I
OUT (max)
V
IN
=6.0V
Supply Current1
Iss1
V
IN
=6.0V, V
CE
=Vss
Supply Current2
Iss2
V
IN
=8.0V, V
CE
=V
IN
EXT Leakage Current
I
LEAK
High
I
CEH
V
CE
=V
IN
CE Level Current
Low
I
CEL
V
CE
=V
ss
V
OUT
V
IN
×V
OUT
Output Voltage Temperature
Characteristics (Note 4)
T
OPR
×V
OUT
Note: 1. V
OUT(T)
=Specified Output Voltage.
2. V
OUT(E)
=Effective Output Voltage (i.e. the output voltage when "V
OUT(T)
+1.0V" is provided at the V
IN
pin while
maintaining a certain I
OUT
value).
3. V
DIFF
= {V
IN1
-V
OUT1
}
*V
OUT1
= A voltage equal to 98% of the Output Voltage whenever an amply stabilized I
OUT
{V
OUT(T)
+1.0V} is
input.
*V
IN1
= The Input Voltage when V
OUT1
appears as Input Voltage is gradually decreased.
4. The characteristics for those parameters marked with an asterisk* are liable to vary depending on which
transistor is used. Please use a transistor with a low saturation voltage level and h
FE
equal to 100 or more.
TEST CONDITIONS
MIN
4.900
1.5
-60
-0.2
TYP
5.000
100
1000
50
-0.05
MAX
5.100
8
8
UNIT
V
V
V
V
V
mV
mV
mA
μA
μA
μA
μA
μA
0.25
60
0.6
80
0.5
0.1
0
Input Stability (Note 4)
I
OUT
=50mA, 6.0V
≤
V
IN
≤
8.0V
0.1
0.3
%/V
V
OUT
I
OUT
=10mA, -20
≤
T
OPR
≤
85
±100
ppm/
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