參數(shù)資料
型號(hào): UC3711QP
英文描述: Low-voltage DC motor speed controller
中文描述: 雙MOSFET驅(qū)動(dòng)器
文件頁數(shù): 1/8頁
文件大?。?/td> 300K
代理商: UC3711QP
UC1714/5
UC2714/5
UC3714/5
FEATURES
Single Input (PWM and TTL
Compatible)
High Current Power FET Driver, 1.0A
Source/2A Sink
Auxiliary Output FET Driver, 0.5A
Source/1A Sink
Time Delays Between Power and
Auxiliary Outputs Independently
Programmable from 50ns to 500ns
Time Delay or True Zero-Voltage
Operation Independently Configurable
for Each Output
Switching Frequency to 1MHz
Typical 50ns Propagation Delays
ENBL Pin Activates 220
μ
A Sleep
Mode
Power Output is Active Low in Sleep
Mode
Synchronous Rectifier Driver
DESCRIPTION
These two families of high speed drivers are designed to provide drive
waveforms for complementary switches. Complementary switch configura-
tions are commonly used in synchronous rectification circuits and active
clamp/reset circuits, which can provide zero voltage switching. In order to
facilitate the soft switching transitions, independently programmable delays
between the two output waveforms are provided on these drivers. The de-
lay pins also have true zero voltage sensing capability which allows imme-
diate activation of the corresponding switch when zero voltage is applied.
These devices require a PWM-type input to operate and can be interfaced
with commonly available PWM controllers.
In the UC1714 series, the AUX output is inverted to allow driving a
p-channel MOSFET. In the UC1715 series, the two outputs are configured
in a true complementary fashion.
6
5
7
8
INPUT
T1
T2
ENBL
S
Q
R
TIMER
V
REF
S
Q
R
TIMER
V
REF
50ns –500ns
50ns –500ns
5V
ENBL
V
CC
3V
GND
BIAS
1.4V
ENABLE
UC1714
ONLY
4
AUX
2
PWR
1
VCC
LOGIC
GATES
TIMER
REF
3
GND
BLOCK DIAGRAM
Complementary Switch FET Drivers
SLUS170A - FEBRUARY 1999 - REVISED JANUARY 2002
UDG-99028
Note: Pin numbers refer to J, N and D packages.
application
INFO
available
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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UC37131N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Peripheral Driver